Invention Grant
- Patent Title: Method, apparatus and system to interconnect packaged integrated circuit dies
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Application No.: US16516695Application Date: 2019-07-19
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Publication No.: US10910347B2Publication Date: 2021-02-02
- Inventor: Yong She , John G. Meyers , Zhicheng Ding , Richard Patten
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Schwabe, Williamson & Wyatt, P.C.
- Main IPC: H01L25/065
- IPC: H01L25/065 ; H01L23/488 ; H01L23/00 ; H01L23/49 ; H01L23/50 ; H01L25/00 ; H01L23/538

Abstract:
Techniques and mechanisms for interconnecting stacked integrated circuit (IC) dies. In an embodiment, a first end of a wire is coupled to a first IC die of a stack, where a second end of the wire is further anchored to the stack independent of the coupled first end. A package material is subsequently disposed around IC dies of the stack and a first portion of the wire that includes the first end. Two-point anchoring of the wire to the stack aids in providing mechanical support to resist movement that might otherwise displace and/or deform the wire while the package material is deposited. In another embodiment, the first portion of the wire is separated from the rest of the wire, and a redistribution layer is coupled to the first portion to enable interconnection between the first IC die and another IC die of the stack.
Public/Granted literature
- US20190341372A1 METHOD, APPARATUS AND SYSTEM TO INTERCONNECT PACKAGED INTEGRATED CIRCUIT DIES Public/Granted day:2019-11-07
Information query
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