- 专利标题： Method for erasing memory cells in a flash memory device using a positive well bias voltage and a negative word line voltage
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申请号： US16583352申请日： 2019-09-26
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公开(公告)号： US10923194B2公开(公告)日： 2021-02-16
- 发明人: Chung-Zen Chen , Yang-Chieh Lin , Chung-Shan Kuo
- 申请人： Conversant Intellectual Property Management Inc.
- 申请人地址： CA Ottawa
- 专利权人： Conversant Intellectual Property Management Inc.
- 当前专利权人： Conversant Intellectual Property Management Inc.
- 当前专利权人地址： CA Ottawa
- 代理机构： Conversant IP Management Corp
- 主分类号： G11C16/14
- IPC分类号： G11C16/14 ; G11C16/16 ; G11C16/04 ; G11C16/08 ; G11C16/02
摘要：
A memory device of the non-volatile type including a memory array having a plurality of memory cells organized as sectors, each sector having a main word line associated with a plurality of local word lines, each local word line coupled to the main word line by a respective local word line driver circuit, each of the local word line driver circuits consisting of a first MOS transistor coupled between the respective main word line and a respective local word line and a second MOS transistor coupled between the respective local word line and a first biasing terminal.
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