- 专利标题: Circuit and method for dynamic clock skew compensation
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申请号: US16808053申请日: 2020-03-03
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公开(公告)号: US10924096B1公开(公告)日: 2021-02-16
- 发明人: Gourav Modi , Chee Chong Chan , Azarudin Abdulla , Riyas Noorudeen Remla
- 申请人: Xilinx, Inc.
- 申请人地址: US CA San Jose
- 专利权人: Xilinx, Inc.
- 当前专利权人: Xilinx, Inc.
- 当前专利权人地址: US CA San Jose
- 代理机构: Craige Thompson, Thompson Patent Law
- 主分类号: H03K5/135
- IPC分类号: H03K5/135 ; H05K1/02 ; G06F1/10 ; H03K5/00
摘要:
Apparatus and associated methods relate to a dynamic lane-to-lane skew reduction technique having (a) a clocking architecture configured to provide a corresponding first delayed clock signal and a corresponding second delayed clock signal through a first and a second plurality of routing traces, respectively, and (b) a number of skew compensation circuits configured to process the corresponding first delayed clock signal and the corresponding second delayed clock signal to generate a corresponding user clock signal for a corresponding lane of a transmitter. In an illustrative example, a first routing trace may transmit a first delayed clock signal in a direction opposite to a second routing trace transmitting a second delayed clock signal. By implementing the technique, each transmitter lane may receive a corresponding user clock signal having substantially the same delay relative to a reference clock signal such that dynamic lane-to-lane skew may be advantageously reduced.
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