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公开(公告)号：US10756748B1
公开(公告)日：2020-08-25
申请号：US16396257
申请日：2019-04-26
申请人： Xilinx, Inc.
摘要： Apparatus and associated methods relate to a circuit that is configured to keep a comparator input voltage stable. In an illustrative example, the circuit may include a first differential path coupled to a first switched-capacitor network's output, a second differential path coupled to a second switched-capacitor network's output. A comparator may have a first input coupled to the first differential path and a second input coupled to the second differential path. The comparator may be controlled by a clock signal to perform comparison. A first capacitor may be coupled from the clock signal to the first differential signal path and a second capacitor may be coupled from the clock signal to the second differential signal path. By introducing the first capacitor and the second capacitor, the comparator input common-mode may keep stable, and the comparator may be less sensitive to kickback effects.
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公开(公告)号：US10778360B1
公开(公告)日：2020-09-15
申请号：US16212391
申请日：2018-12-06
申请人： Xilinx, Inc.
发明人： Lifeng Wang , Jinhua Li , Yong Hu
摘要： Apparatus and associated methods relate to high accuracy timestamp support by controlling a first phase relationship between an outbound signal transmitted by a transmitting circuit and a local reference clock signal, measuring a second phase difference between a received data signal and the local reference signal, and measuring a third phase difference between a received time of day (RXTOD) signal and the local reference signal. In an illustrative example, a state machine circuit may be operated to control the first phase relationship, a phase measuring circuit may be configured to measure the second phase difference and the third phase difference. By comparing results obtained from phase control and phase measurement, the time of day (TOD) of each transmitted/received bit can be calculated at 1-bit level accuracy and achieve 1-bit level accuracy in the timestamp.
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公开(公告)号：US10862500B1
公开(公告)日：2020-12-08
申请号：US16683731
申请日：2019-11-14
申请人： Xilinx, Inc.
摘要： Apparatus and associated methods relate to maintaining a total current of a switch cell in a digital-to-analog converter at a controllable operating point by adjusting shunt current control signals applied to programmable shunt current sources in opposite polarity with respect to a tail current control signal applied to a programmable tail current source. In an illustrative example, the total current may flow through differential legs of a switch cell. The programmable shunt current sources may, for example, be configured to compensate for adjustments to the programmable tail current source. In an illustrative example, tail current and shunt currents may flow through a pair of cascode transistors. In various examples, controlling the programmable shunt current sources to compensate adjustments to the tail current source may, for example, permit controlled common mode voltage or operating point so as to reduce device voltage stress over a wider dynamic range of output voltages.
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公开(公告)号：US10763879B1
公开(公告)日：2020-09-01
申请号：US16526000
申请日：2019-07-30
申请人： Xilinx, Inc.
发明人： Pedro W. Neto
摘要： Apparatus and associated methods relate to a clock generation circuit which generates asynchronous clock signals for a successive approximation ADC architecture based on time-interleaved comparators. In an illustrative example, a circuit may include (a) a first comparator configured to receive an input signal and generate a first ready signal to indicate a comparison decision being complete, (b) a second comparator configured to receive the input signal and generate a second ready signal to indicate a comparison decision being complete, and (c) a clock generation circuit coupled to receive the first and the second ready signals and generate a first clock for the first comparator and a second clock for the second comparator. The first and the second clock signals may be in anti-phase. Thus, each comparator may have enough time to reach a valid comparison in each successive approximation cycle, and kickback noises at comparator' inputs may be advantageously reduced.
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公开(公告)号：US11133963B1
公开(公告)日：2021-09-28
申请号：US17011595
申请日：2020-09-03
申请人： Xilinx, Inc.
发明人： Kevin Zheng , Ronan Casey
摘要： Apparatus and associated methods relate to targeted digital correction of a predetermined component of inter-symbol interference (ISI) associated with two or more ranks of cascaded track-and-hold (T/H) front-end circuits of a Time-Interleaved analog-to-digital converter (TI-ADC). In an illustrative example, for two T/H circuit ranks of size N and M, the predetermined component to be compensated may be located at (N×M)th unit interval (UI). A feed forward equalizer (FFE) and/or a decision feedback equalizer (DFE) in a digital signal processing system (DSP) may be then configured to have extra taps and corresponding expanded equalization ranges to mitigate the ISI. Thus, a deterministic ISI component at the N×Mth UI may be digitally corrected by providing equalization with N×M taps at low cost to facilitate scaling to higher bit rates.
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公开(公告)号：US10924096B1
公开(公告)日：2021-02-16
申请号：US16808053
申请日：2020-03-03
申请人： Xilinx, Inc.
摘要： Apparatus and associated methods relate to a dynamic lane-to-lane skew reduction technique having (a) a clocking architecture configured to provide a corresponding first delayed clock signal and a corresponding second delayed clock signal through a first and a second plurality of routing traces, respectively, and (b) a number of skew compensation circuits configured to process the corresponding first delayed clock signal and the corresponding second delayed clock signal to generate a corresponding user clock signal for a corresponding lane of a transmitter. In an illustrative example, a first routing trace may transmit a first delayed clock signal in a direction opposite to a second routing trace transmitting a second delayed clock signal. By implementing the technique, each transmitter lane may receive a corresponding user clock signal having substantially the same delay relative to a reference clock signal such that dynamic lane-to-lane skew may be advantageously reduced.
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