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公开(公告)号：US09083347B1
公开(公告)日：2015-07-14
申请号：US14280188
申请日：2014-05-16
Applicant: Xilinx, Inc.
Inventor： Riyas Noorudeen Remla , Rajesh Bansal
IPC: H03K21/38
CPC classification number: H03K21/38
Abstract: Circuits and methods for capturing internal signal values in a circuit before, during, and after a trigger event are disclosed. For example, a circuit can include a shift register configured to receive data values of an input data set over a plurality of cycles, and a counter unit configured to receive a trigger signal and to output the trigger signal after a number of cycles following the receiving of the trigger signal, where the trigger signal indicates a trigger event. The circuit can also include a switch configured to receive the trigger signal from the counter unit and to open a connection between an input interface and the shift register in response to receiving the trigger signal.
Abstract translation: 公开了在触发事件之前，期间和之后捕获电路中的内部信号值的电路和方法。 例如，电路可以包括被配置为在多个周期中接收输入数据集的数据值的移位寄存器，以及被配置为接收触发信号并且在接收之后的多个周期之后输出触发信号的计数器单元 触发信号，其中触发信号指示触发事件。 电路还可以包括被配置为从计数器单元接收触发信号并且响应于接收到触发信号而打开输入接口和移位寄存器之间的连接的开关。
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公开(公告)号：US12248761B2
公开(公告)日：2025-03-11
申请号：US18129762
申请日：2023-03-31
Applicant: XILINX, INC.
Inventor： Riyas Noorudeen Remla , Warren E. Cory
Abstract: Embodiments herein describe a solution for deterministic de-assertion of write and read resets of an asynchronous gearbox FIFO having unequal write and read data bit widths. Proposed approaches look for a stable region between read and write clock phases by sweeping one of the clock phases until the leading edges (phases) of both clocks are aligned then releasing the write and read resets deterministically based upon a change in cyclic behavior of detected logic levels of a reset beacon waveform.
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公开(公告)号：US10033523B1
公开(公告)日：2018-07-24
申请号：US15676667
申请日：2017-08-14
Applicant: Xilinx, Inc.
Inventor： Riyas Noorudeen Remla , Warren E. Cory
Abstract: A circuit for measuring latency in an integrated circuit device is described. The circuit comprises a transmitter circuit having signal generator configured to generate a test signal having a marker for determining a latency in a path associated with the integrated circuit device; and a latency calculation circuit coupled to the signal generator and having a latency adjustment circuit and a unit interval (UI) adjustment circuit; wherein the latency calculation circuit generates a latency value (LATENCY) based upon a latency count from the latency adjustment circuit and a UI adjustment from the UI adjustment circuit.
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Patent Agency Ranking
公开(公告)号：US11314277B1
公开(公告)日：2022-04-26
申请号：US16532293
申请日：2019-08-05
Applicant: XILINX, INC.
Inventor： Riyas Noorudeen Remla , Gourav Modi , Azarudin Abdulla , Chee Chong Chan
Abstract: Examples described herein provide a method for reducing lane-to-lane serial skew in an integrated circuit. In an example using a processor-based system, a maximum clock skew is determined from clock skews of respective lanes of a transmitter of the IC. Each of the clock skews corresponds to a skew of a clock signal of the respective lane relative to a same reference clock signal. A skew match amount is determined for each lane of the lanes of the transmitter. The skew match amount for a respective lane of the lanes is based on the maximum clock skew and the clock skew of the respective lane. Configuration data is generated to configure the transmitter to shift incoming data for each lane of the lanes based on the skew match amount for the respective lane.
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公开(公告)号：US10924096B1
公开(公告)日：2021-02-16
申请号：US16808053
申请日：2020-03-03
Applicant: Xilinx, Inc.
Inventor： Gourav Modi , Chee Chong Chan , Azarudin Abdulla , Riyas Noorudeen Remla
Abstract: Apparatus and associated methods relate to a dynamic lane-to-lane skew reduction technique having (a) a clocking architecture configured to provide a corresponding first delayed clock signal and a corresponding second delayed clock signal through a first and a second plurality of routing traces, respectively, and (b) a number of skew compensation circuits configured to process the corresponding first delayed clock signal and the corresponding second delayed clock signal to generate a corresponding user clock signal for a corresponding lane of a transmitter. In an illustrative example, a first routing trace may transmit a first delayed clock signal in a direction opposite to a second routing trace transmitting a second delayed clock signal. By implementing the technique, each transmitter lane may receive a corresponding user clock signal having substantially the same delay relative to a reference clock signal such that dynamic lane-to-lane skew may be advantageously reduced.
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公开(公告)号：US20250044827A1
公开(公告)日：2025-02-06
申请号：US18364336
申请日：2023-08-02
Applicant: Xilinx, Inc.
Inventor： Riyas Noorudeen Remla
Abstract: A system for clock variation measurement includes a first clock counter circuit configured to generate a plurality of first counts of a first clock signal, a second clock counter circuit configured to generate a plurality of second counts of a second clock signal, a first synchronizer circuit configured to synchronize the plurality of first counts according to a third clock signal, and a second synchronizer circuit configured to synchronize the plurality of second counts according to the third clock signal. The system includes a difference circuit configured to generate a plurality of differences from respective count pairs as synchronized. The system includes a variation circuit configured to generate a variation signal indicating an amount of variation between the first clock signal and the second clock signal based, at least in part, on the plurality of differences.
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公开(公告)号：US11681844B1
公开(公告)日：2023-06-20
申请号：US17216508
申请日：2021-03-29
Applicant: XILINX, INC.
Inventor： Riyas Noorudeen Remla , Chee Chong Chan
IPC: G06F30/333 , G06F30/31 , G06F119/02
CPC classification number: G06F30/333 , G06F30/31 , G06F2119/02
Abstract: A semiconductor device comprises a design under test (DUT), a testing interface, pattern generation circuitry, and pattern checker circuitry. The pattern generation circuitry is connected to the DUT and the testing interface. The pattern generation circuitry is configured to generate a test data sequence and control data based on configuration data received from the testing interface, and communicate the test data sequence and the control data to the DUT. The pattern checker circuitry is connected to the DUT and the testing interface. The pattern checker circuitry is configured to generate a comparison test sequence based on the configuration data received from the testing interface, receive resultant test data sequence and output control data from the DUT, and generate a first error signal based on a comparison of the resultant test data sequence and the comparison test sequence and a comparison of the output control data and the configuration data.
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公开(公告)号：US10161999B1
公开(公告)日：2018-12-25
申请号：US15091376
申请日：2016-04-05
Applicant: Xilinx, Inc.
Inventor： Heera Nand , Niloy Roy , Mahesh Sankroj , Siddharth Rele , Riyas Noorudeen Remla , Rajesh Bansal , Bradley K. Fross
IPC: G06F17/50 , G01R31/317 , G01R31/3177
Abstract: Approaches for capturing states of signals of a circuit-under-test are disclosed. A logic analyzer circuit is coupled to the circuit-under-test and is configured to receive a plurality of probe signals and a plurality of trigger signals from the circuit-under-test. The logic analyzer circuit inputs data identifying a subset of the probe signals and a subset of the trigger signals. The logic analyzer circuit selects the subset of trigger signals for input to trigger logic and selects the subset of probe signals in the logic analyzer circuit after the logic analyzer circuit and the circuit-under-test are active. The logic analyzer circuit samples states of the subset of probe signals in response to the trigger logic and stores the sampled states of the subset of probe signals in a memory.
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