A three-dimensional calibration structure for measuring buried defects on a semiconductor device is disclosed. The three-dimensional calibration structure includes a defect standard wafer (DSW) including one or more programmed surface defects. The three-dimensional calibration structure includes a planarized layer deposited on the DSW. The three-dimensional calibration structure includes a layer stack deposited on the planarized layer. The layer stack includes two or more alternating layers. The three-dimensional calibration structure includes a cap layer deposited on the layer stack. One or more air gaps are formed in the layer stack following deposition of the cap layer. The three-dimensional calibration structure includes one or more holes formed into at least one of the cap layer, the layer stack, or the planarized layer.