Invention Grant
- Patent Title: Self-aligned spacers for multi-gate devices and method of fabrication thereof
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Application No.: US16358314Application Date: 2019-03-19
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Publication No.: US10930794B2Publication Date: 2021-02-23
- Inventor: Kuo-Cheng Ching , Shi Ning Ju , Guan-Lin Chen , Kuan-Lun Cheng , Chih-Hao Wang
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Haynes and Boone, LLP
- Main IPC: H01L29/786
- IPC: H01L29/786 ; H01L29/66 ; H01L29/423 ; H01L29/40 ; H01L21/02

Abstract:
A method of fabricating a semiconductor device includes forming a fin extruding from a substrate, the fin having a plurality of sacrificial layers and a plurality of channel layers, wherein the sacrificial layers and the channel layers are alternately arranged; removing a portion of the sacrificial layers from a channel region of the fin; depositing a spacer material in areas from which the portion of the sacrificial layers have been removed; selectively removing a portion of the spacer material, thereby exposing the channel layers in the channel region of the fin, wherein other portions of the spacer material remain as a spacer feature; and forming a gate structure engaging the exposed channel layers.
Public/Granted literature
- US20200006577A1 Self-Aligned Spacers for Multi-Gate Devices and Method of Fabrication Thereof Public/Granted day:2020-01-02
Information query
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