- Patent Title: Method and structure of cut end with self-aligned double patterning
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Application No.: US16571407Application Date: 2019-09-16
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Publication No.: US10937652B1Publication Date: 2021-03-02
- Inventor: Hsi-Wen Tien , Wei-Hao Liao , Pin-Ren Dai , Chih Wei Lu , Chung-Ju Lee
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsinchu
- Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee Address: TW Hsinchu
- Agency: Haynes and Boone, LLP
- Main IPC: H01L21/033
- IPC: H01L21/033 ; H01L21/768

Abstract:
Semiconductor device and the manufacturing method thereof are disclosed herein. An exemplary method of forming a semiconductor device comprises receiving a structure including a substrate and a first hard mask over the substrate, the first hard mask having at least two separate portions; forming spacers along sidewalls of the at least two portions of the first hard mask with a space between the spacers; forming a second hard mask in the space; forming a first cut in the at least two portions of the first hard mask; forming a second cut in the second hard mask; and depositing a cut hard mask in the first cut and the second cut.
Public/Granted literature
- US20210082698A1 Method and Structure of Cut End with Self-Aligned Double Patterning Public/Granted day:2021-03-18
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