发明授权
- 专利标题: Data flow graph optimization techniques for RTL loops with conditional-exit statements
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申请号: US16733568申请日: 2020-01-03
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公开(公告)号: US10943042B1公开(公告)日: 2021-03-09
- 发明人: Sumanta Datta , Aman Gayasen
- 申请人: Xilinx, Inc.
- 申请人地址: US CA San Jose
- 专利权人: Xilinx, Inc.
- 当前专利权人: Xilinx, Inc.
- 当前专利权人地址: US CA San Jose
- 代理机构: Amir Tabarrok, Rimon Law Firm Evolved
- 主分类号: G06F30/337
- IPC分类号: G06F30/337 ; H03K19/17748 ; G06F119/12
摘要:
A computer-implemented method includes compiling a Register Transfer Level (RTL) code to form a data flow graph (DFG). The computer-implemented method includes identifying a chain of multiplexers in the DFG, wherein the chain of multiplexers includes exit multiplexers associated with a loop exit path and non-exit multiplexers. The computer-implemented method also includes traversing a topological order of the DFG in reverse. The computer-implemented method also includes computing fanin-cones for each two consecutive exit multiplexers. The computer-implemented method includes generating a truth table responsive to valid fanin-cones and back propagating select conditions for the each two consecutive exit multiplexers. The computer-implemented method includes eliminating an exit multiplexer from the each two consecutive exit multiplexers based on the truth table. The computer-implemented method further includes transforming the DFG to a new DFG based on the truth table.
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