公开(公告)号：US20230161569A1

公开(公告)日：2023-05-25

申请号：US17456002

申请日：2021-11-22

Applicant: Xilinx, Inc.

Inventor： Sumanta Datta ,  Srijan Tiwary ,  Aman Gayasen

IPC: G06F8/36 ,  G06F8/41 ,  G06F8/20 ,  G06F8/75

CPC classification number: G06F8/36 ,  G06F8/44 ,  G06F8/20 ,  G06F8/75

Abstract: Implementing an application for a data processing engine (DPE) array can include detecting, using computer hardware, a component of a hardware library package instantiated by an application. The application is specified in source code and is configured to execute on a DPE array. An instance of the component is extracted from the application. The extracted instance specifies values of parameters for the instance of the component. The instance can be partitioned by generating program code defining one or more kernels corresponding to the instance of the component. The partitioning is based on a defined performance metric of the component and a defined performance requirement of the application. The application is transformed by replacing the instance of the component with the program code generated by the partitioning. The application, as transformed, is compiled into program code executable by the DPE array.

公开(公告)号：US11586791B1

公开(公告)日：2023-02-21

申请号：US17480389

申请日：2021-09-21

Applicant: Xilinx, Inc.

Inventor： Anup Hosangadi ,  Aman Gayasen ,  Srinivasan Dasasathyan ,  Padmini Gopalakrishnan

IPC: G06F30/31 ,  G06F30/394

Abstract: Approaches for visualizing data buses in a circuit design include determining ones of the data buses that satisfy selection criteria. For each element connected to a data bus of the ones of the data buses, a method and system determine whether the element is of interest or the element is not of interest. A graphical representation of the ones of the data buses and each element of interest is generated, and data buses of the circuit design determined to not satisfy the selection criteria and elements not of interest are excluded from the graphical representation. The graphical representation is displayed on a display device.

公开(公告)号：US10586005B1

公开(公告)日：2020-03-10

申请号：US15927846

申请日：2018-03-21

Applicant: Xilinx, Inc.

Inventor： Kameshwar Chandrasekar ,  Surya Pratik Saha ,  Aman Gayasen ,  Sumanta Datta

IPC: G06F17/50

Abstract: Incremental synthesis for changes to a circuit design can include synthesizing, using computer hardware, a first circuit design resulting in a partitioning of the first circuit design and a plurality of synthesized partitions of the first circuit design and, for a second circuit design that is a modified version of the first circuit design and based upon the partitioning of the first circuit design, determining, using the computer hardware, a partition of the second circuit design that differs from the first circuit design. The partition of the second circuit design can be technology mapped using the computer hardware resulting in a synthesized partition of the second circuit design. A synthesized circuit design corresponding to the second circuit design can be generated using the computer hardware by combining synthesized partitions of the plurality of synthesized partitions of the first circuit design that are unchanged relative to the second circuit design with the synthesized partition of the second circuit design.

公开(公告)号：US11829733B2

公开(公告)日：2023-11-28

申请号：US17456002

申请日：2021-11-22

Applicant: Xilinx, Inc.

Inventor： Sumanta Datta ,  Srijan Tiwary ,  Aman Gayasen

IPC: G06F8/36 ,  G06F8/75 ,  G06F8/20 ,  G06F8/41

CPC classification number: G06F8/36 ,  G06F8/20 ,  G06F8/44 ,  G06F8/75

Abstract: Implementing an application for a data processing engine (DPE) array can include detecting, using computer hardware, a component of a hardware library package instantiated by an application. The application is specified in source code and is configured to execute on a DPE array. An instance of the component is extracted from the application. The extracted instance specifies values of parameters for the instance of the component. The instance can be partitioned by generating program code defining one or more kernels corresponding to the instance of the component. The partitioning is based on a defined performance metric of the component and a defined performance requirement of the application. The application is transformed by replacing the instance of the component with the program code generated by the partitioning. The application, as transformed, is compiled into program code executable by the DPE array.

公开(公告)号：US11768663B1

公开(公告)日：2023-09-26

申请号：US17014410

申请日：2020-09-08

Applicant: Xilinx, Inc.

Inventor： Srijan Tiwary ,  Aman Gayasen

IPC: G06F7/506 ,  G06F30/327 ,  G06F30/34 ,  G06F7/533 ,  G06F7/57

CPC classification number: G06F7/5334 ,  G06F7/506 ,  G06F7/57 ,  G06F30/327 ,  G06F30/34

Abstract: Approaches for logic compaction include inputting an optimization directive that specifies one of area optimization or speed optimization to a synthesis tool executing on a computer processor. The synthesis tool identifies a multiplier and/or an adder specified in a circuit design and synthesizing the multiplier into logic having LUT-to-LUT connections between LUTs on separate slices of a programmable integrated circuit (IC) in response to the optimization directive specifying speed optimization. The synthesis tool synthesizes the multiplier and/or adder into logic having LUT-carry connections between LUTs and carry logic within a single slice of the programmable IC in response to the optimization directive specifying area optimization. The method includes implementing a circuit on the programmable IC from the logic having LUT-carry connections in response to the optimization directive specifying area optimization.

公开(公告)号：US20240193341A1

公开(公告)日：2024-06-13

申请号：US18078540

申请日：2022-12-09

Applicant: Xilinx, Inc.

Inventor： Veeresh Pratap Singh ,  Mohit Sharma ,  Chatla Surya Phanindra ,  Sandip Maity ,  Aman Gayasen ,  Srinivasan Dasasathyan

IPC: G06F30/398 ,  G06F30/392 ,  G06F30/394

CPC classification number: G06F30/398 ,  G06F30/392 ,  G06F30/394

Abstract: Placement of macros of a circuit design includes mapping the macros to types of sub-circuits of an integrated circuit (IC). The IC includes anchors and instances of each type of the types of sub-circuits. The macros are grouped based on couplings of the macros to the anchors specified in the circuit design. Each group includes one or more macros, and the one or more macros in each group are all coupled to the same set of one or more anchors. A location is selected from alternative locations for each group of macros based on a distance of the location from the same set of anchors. Each location includes one or more instances of one or more types of the types of sub-circuits. The circuit design is placed and routed after selecting the location for each group, and implementation data is generated for making an IC that implements the circuit design.

公开(公告)号：US10534885B1

公开(公告)日：2020-01-14

申请号：US15927831

申请日：2018-03-21

Applicant: Xilinx, Inc.

Inventor： Sumanta Datta ,  Anup Hosangadi ,  Aman Gayasen

IPC: G06F17/50

Abstract: Range information is determined for each variable of a circuit design. The range information is propagated from inputs to outputs of nodes of a DFG representation of the circuit design. For each multiplexer of the circuit design represented as a multiplexer node in the DFG, whether range information associated with a selector input of the multiplexer node restricts selection of data inputs of the multiplexer node to only one selected data input of the multiplexer node is determined. In response to determining that range information associated with the selector input restricts selection of data inputs to only one data input, the DFG is modified by connecting the selected data input to each load of the multiplexer node, and removing the multiplexer node, a corresponding select logic node of the multiplexer node, and nodes connected to unselected data inputs of the multiplexer node.

公开(公告)号：US10331836B1

公开(公告)日：2019-06-25

申请号：US15730431

申请日：2017-10-11

Applicant: Xilinx, Inc.

Inventor： Anup Hosangadi ,  Sumanta Datta ,  Aman Gayasen ,  Ashish Sirasao

IPC: G06F17/50 ,  H03K19/173

Abstract: Implementing a circuit design can include determining a chain of a plurality of loop elements of a circuit design, wherein each loop element includes a bit select node configured to perform a bit assignment operation and a corresponding address calculation node, wherein the address calculation nodes use a common variable to calculate a starting bit location provided to the corresponding bit select node. In response to the determining, the chain is replicated resulting in one chain for each value of the common variable and transforming each chain into a plurality of wires. A multiplexer is inserted into the circuit design. The plurality of wires for each chain is coupled to inputs of the multiplexer and the common variable is provided to the multiplexer as a select signal.

公开(公告)号：US08984462B1

公开(公告)日：2015-03-17

申请号：US14249601

申请日：2014-04-10

Applicant: Xilinx, Inc.

Inventor： Sabyasachi Das ,  Ruibing Lu ,  Zhiyong Wang ,  Aman Gayasen

IPC: G06F17/50

CPC classification number: G06F17/5054 ,  G06F2217/84

Abstract: Physical optimization for timing closure for an integrated circuit includes processing a circuit design at least partially through a design flow to a late stage of the design flow. Using a processor, a baseline delay is calculated for each of a plurality of paths of the circuit design. A slack for each of the plurality of paths is determined. Physical optimization further includes selecting a path of the circuit design that meets a selection criterion according, at least in part, to the slack of the path, applying, using the processor, a physical optimization to the selected path resulting in an optimized path, and calculating a delay of the optimized path. The optimized path is incorporated into the circuit design only responsive to determining that the delay of the optimized path is less than the baseline delay of the selected path.

Abstract translation: 用于集成电路的时序闭合的物理优化包括至少部分地通过设计流处理电路设计到设计流程的后期阶段。 使用处理器，为电路设计的多个路径中的每一个计算基线延迟。 确定多个路径中的每一个的松弛。 物理优化进一步包括至少部分地根据路径的松弛来选择满足选择标准的电路设计的路径，使用处理器对所选择的路径应用物理优化，得到优化的路径，以及 计算优化路径的延迟。 优化的路径被合并到电路设计中，仅响应于确定优化路径的延迟小于所选路径的基线延迟。

公开(公告)号：US20250077760A1

公开(公告)日：2025-03-06

申请号：US18461992

申请日：2023-09-06

Applicant: Xilinx, Inc.

Inventor： Sandip Maity ,  Chun Zhang ,  Aman Gayasen

IPC: G06F30/398

Abstract: Control set optimization for a circuit design includes generating, by a processor, Observability Don't Care (ODC) expressions for registers of the circuit design. Redundant reset pins of the registers of the circuit design are determined by the processor by iteratively checking, on a per-cube and a per-literal basis for each ODC expression, whether a value of a literal causes the ODC expression to evaluate to 1. A modified version of the circuit design is generated by the processor by connecting one or more reset pins of the set of redundant reset pins to one or more constants.