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1.发明公开公开(公告)号：US20230161569A1
公开(公告)日：2023-05-25
申请号：US17456002
申请日：2021-11-22
申请人： Xilinx, Inc.
发明人： Sumanta Datta , Srijan Tiwary , Aman Gayasen
摘要： Implementing an application for a data processing engine (DPE) array can include detecting, using computer hardware, a component of a hardware library package instantiated by an application. The application is specified in source code and is configured to execute on a DPE array. An instance of the component is extracted from the application. The extracted instance specifies values of parameters for the instance of the component. The instance can be partitioned by generating program code defining one or more kernels corresponding to the instance of the component. The partitioning is based on a defined performance metric of the component and a defined performance requirement of the application. The application is transformed by replacing the instance of the component with the program code generated by the partitioning. The application, as transformed, is compiled into program code executable by the DPE array.
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公开(公告)号：US10586005B1
公开(公告)日：2020-03-10
申请号：US15927846
申请日：2018-03-21
申请人： Xilinx, Inc.
IPC分类号： G06F17/50
摘要： Incremental synthesis for changes to a circuit design can include synthesizing, using computer hardware, a first circuit design resulting in a partitioning of the first circuit design and a plurality of synthesized partitions of the first circuit design and, for a second circuit design that is a modified version of the first circuit design and based upon the partitioning of the first circuit design, determining, using the computer hardware, a partition of the second circuit design that differs from the first circuit design. The partition of the second circuit design can be technology mapped using the computer hardware resulting in a synthesized partition of the second circuit design. A synthesized circuit design corresponding to the second circuit design can be generated using the computer hardware by combining synthesized partitions of the plurality of synthesized partitions of the first circuit design that are unchanged relative to the second circuit design with the synthesized partition of the second circuit design.
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3.发明授权公开(公告)号：US11829733B2
公开(公告)日：2023-11-28
申请号：US17456002
申请日：2021-11-22
申请人： Xilinx, Inc.
发明人： Sumanta Datta , Srijan Tiwary , Aman Gayasen
摘要： Implementing an application for a data processing engine (DPE) array can include detecting, using computer hardware, a component of a hardware library package instantiated by an application. The application is specified in source code and is configured to execute on a DPE array. An instance of the component is extracted from the application. The extracted instance specifies values of parameters for the instance of the component. The instance can be partitioned by generating program code defining one or more kernels corresponding to the instance of the component. The partitioning is based on a defined performance metric of the component and a defined performance requirement of the application. The application is transformed by replacing the instance of the component with the program code generated by the partitioning. The application, as transformed, is compiled into program code executable by the DPE array.
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公开(公告)号：US10534885B1
公开(公告)日：2020-01-14
申请号：US15927831
申请日：2018-03-21
申请人： Xilinx, Inc.
发明人： Sumanta Datta , Anup Hosangadi , Aman Gayasen
IPC分类号： G06F17/50
摘要： Range information is determined for each variable of a circuit design. The range information is propagated from inputs to outputs of nodes of a DFG representation of the circuit design. For each multiplexer of the circuit design represented as a multiplexer node in the DFG, whether range information associated with a selector input of the multiplexer node restricts selection of data inputs of the multiplexer node to only one selected data input of the multiplexer node is determined. In response to determining that range information associated with the selector input restricts selection of data inputs to only one data input, the DFG is modified by connecting the selected data input to each load of the multiplexer node, and removing the multiplexer node, a corresponding select logic node of the multiplexer node, and nodes connected to unselected data inputs of the multiplexer node.
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公开(公告)号：US10331836B1
公开(公告)日：2019-06-25
申请号：US15730431
申请日：2017-10-11
申请人： Xilinx, Inc.
发明人： Anup Hosangadi , Sumanta Datta , Aman Gayasen , Ashish Sirasao
IPC分类号： G06F17/50 , H03K19/173
摘要： Implementing a circuit design can include determining a chain of a plurality of loop elements of a circuit design, wherein each loop element includes a bit select node configured to perform a bit assignment operation and a corresponding address calculation node, wherein the address calculation nodes use a common variable to calculate a starting bit location provided to the corresponding bit select node. In response to the determining, the chain is replicated resulting in one chain for each value of the common variable and transforming each chain into a plurality of wires. A multiplexer is inserted into the circuit design. The plurality of wires for each chain is coupled to inputs of the multiplexer and the common variable is provided to the multiplexer as a select signal.
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公开(公告)号：US20240193225A1
公开(公告)日：2024-06-13
申请号：US18065491
申请日：2022-12-13
申请人： Xilinx, Inc.
发明人： Srijan Tiwary , Fan Zhang , Sumanta Datta , Aman Gayasen
CPC分类号： G06F17/16 , G06F7/4876 , G06F7/727
摘要： Parameters defining a matrix multiply operation to be implemented in a data processing array can be received. A formulation of the matrix multiply operation is generated based on the parameters. A matrix multiply solution is determined for performing the matrix multiply operation in the data processing array. The matrix multiply solution specifies a spatial and temporal partitioning of the matrix multiply operation for implementation in the data processing array. Synthesizable program code is generated that defines an interface for the data processing array based on the matrix multiply solution. The interface is configured to partition and transfer input data to the data processing array from an external memory and convey output data from the data processing array to the external memory.
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公开(公告)号：US11755801B1
公开(公告)日：2023-09-12
申请号：US17107367
申请日：2020-11-30
申请人： Xilinx, Inc.
IPC分类号： G06F30/3312
CPC分类号： G06F30/3312
摘要： Implementing a circuit design within an integrated circuit can include converting the circuit design, specified in a hardware description language, into a data flow graph and creating range set data structures in a memory. The range set data structures correspond to nodes of the data flow graph. Each range set data structure can be initialized with a range of values the corresponding node can take as specified by the circuit design. The method can include determining actual values the nodes are capable of taking by propagating the values through the data flow graph. The range set data structures are updated to store the actual values for the corresponding nodes. The method also can include modifying a selected node of the data flow graph based on the actual values stored in the range set data structure of the selected node and semantics of the selected node.
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公开(公告)号：US10943042B1
公开(公告)日：2021-03-09
申请号：US16733568
申请日：2020-01-03
申请人： Xilinx, Inc.
发明人： Sumanta Datta , Aman Gayasen
IPC分类号： G06F30/337 , H03K19/17748 , G06F119/12
摘要： A computer-implemented method includes compiling a Register Transfer Level (RTL) code to form a data flow graph (DFG). The computer-implemented method includes identifying a chain of multiplexers in the DFG, wherein the chain of multiplexers includes exit multiplexers associated with a loop exit path and non-exit multiplexers. The computer-implemented method also includes traversing a topological order of the DFG in reverse. The computer-implemented method also includes computing fanin-cones for each two consecutive exit multiplexers. The computer-implemented method includes generating a truth table responsive to valid fanin-cones and back propagating select conditions for the each two consecutive exit multiplexers. The computer-implemented method includes eliminating an exit multiplexer from the each two consecutive exit multiplexers based on the truth table. The computer-implemented method further includes transforming the DFG to a new DFG based on the truth table.
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