Invention Grant
- Patent Title: Etch-stop layer topography for advanced integrated circuit structure fabrication
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Application No.: US16509398Application Date: 2019-07-11
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Publication No.: US10943817B2Publication Date: 2021-03-09
- Inventor: Andrew W. Yeoh , Ruth Brain , Michael L. Hattendorf , Christopher P. Auth
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Schwabe, Williamson & Wyatt, P.C.
- Main IPC: H01L21/44
- IPC: H01L21/44 ; H01L21/768 ; H01L23/522 ; H01L23/528 ; H01L23/532 ; H01L27/092 ; H01L21/8238 ; H01L21/8234 ; H01L29/78 ; H01L29/66 ; H01L27/088 ; H01L29/165

Abstract:
Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a plurality of conductive interconnect lines in and spaced apart by an inter-layer dielectric (ILD) layer above a substrate. Individual ones of the plurality of conductive interconnect lines have an upper surface below an upper surface of the ILD layer. An etch-stop layer is on and conformal with the ILD layer and the plurality of conductive interconnect lines, the etch-stop layer having a non-planar upper surface with an uppermost portion of the non-planar upper surface over the ILD layer and a lowermost portion of the non-planar upper surface over the plurality of conductive interconnect lines.
Public/Granted literature
- US20200027781A1 ETCH-STOP LAYER TOPOGRAPHY FOR ADVANCED INTEGRATED CIRCUIT STRUCTURE FABRICATION Public/Granted day:2020-01-23
Information query
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