公开(公告)号：US10943817B2

公开(公告)日：2021-03-09

申请号：US16509398

申请日：2019-07-11

Applicant: Intel Corporation

Inventor： Andrew W. Yeoh ,  Ruth Brain ,  Michael L. Hattendorf ,  Christopher P. Auth

IPC: H01L21/44 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L27/092 ,  H01L21/8238 ,  H01L21/8234 ,  H01L29/78 ,  H01L29/66 ,  H01L27/088 ,  H01L29/165

Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a plurality of conductive interconnect lines in and spaced apart by an inter-layer dielectric (ILD) layer above a substrate. Individual ones of the plurality of conductive interconnect lines have an upper surface below an upper surface of the ILD layer. An etch-stop layer is on and conformal with the ILD layer and the plurality of conductive interconnect lines, the etch-stop layer having a non-planar upper surface with an uppermost portion of the non-planar upper surface over the ILD layer and a lowermost portion of the non-planar upper surface over the plurality of conductive interconnect lines.

公开(公告)号：US11723188B2

公开(公告)日：2023-08-08

申请号：US16024578

申请日：2018-06-29

Applicant: Intel Corporation

Inventor： Uygar Avci ,  Ian Young ,  Daniel Morris ,  Seiyon Kim ,  Yih Wang ,  Ruth Brain

IPC: H01L23/522 ,  H01L21/768 ,  H10B12/00 ,  H01L49/02

CPC classification number: H10B12/315 ,  H01L21/76808 ,  H01L21/76843 ,  H01L23/5226 ,  H01L28/91 ,  H10B12/033 ,  H10B12/50

Abstract: Embodiments include an embedded dynamic random access memory (DRAM) device, a method of forming an embedded DRAM device, and a memory device. An embedded DRAM device includes a dielectric having a logic area and a memory area, and a trace and a via disposed in the logic area of dielectric. The embedded DRAM device further includes ferroelectric capacitors disposed in the memory area of dielectric, where each ferroelectric capacitor includes a first electrode, a ferroelectric layer, and a second electrode, and where the ferroelectric layer surrounds the first electrode of each ferroelectric capacitor and extends along a top surface of the dielectric in the memory area. The embedded DRAM device includes an etch stop layer above the dielectric. The second etch stop in the logic area may have a z-height that is approximately equal to a z-height of a top surface of the second etch stop in the memory area.

公开(公告)号：US20250006721A1

公开(公告)日：2025-01-02

申请号：US18215514

申请日：2023-06-28

Applicant: Intel Corporation

Inventor： Sukru Yemenicioglu ,  Douglas Stout ,  Tai-Hsuan Wu ,  Xinning Wang ,  Ruth Brain ,  Chin-Hsuan Chen ,  Sivakumar Venkataraman ,  Quan Shi ,  Nikolay Ryzhenko Vladimirovich

IPC: H01L27/02 ,  G06F30/392 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775

Abstract: Techniques are described for designing and forming cells comprising transistor devices for an integrated circuit. In an example, an integrated circuit structure includes a plurality of cells arranged in rows where some rows have different cell heights compared to other rows. Additionally, the various rows of cells may contain semiconductor nanoribbons having different widths between different rows. For example, any number of first rows of cells can each have a first height and any number of second rows can each have a second height that is smaller than the first height. The first rows of cells may include transistors with semiconductor nanoribbons having a first width and the second rows of cells may include transistors with semiconductor nanoribbons having a second width smaller than the first width. In some cases, any of the first rows of cells may also include transistors with semiconductor nanoribbons having the second width.

公开(公告)号：US10796951B2

公开(公告)日：2020-10-06

申请号：US15859417

申请日：2017-12-30

Applicant: Intel Corporation

Inventor： Andrew W. Yeoh ,  Ruth Brain ,  Michael L. Hattendorf ,  Christopher P. Auth

IPC: H01L21/44 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L21/8234 ,  H01L29/78 ,  H01L29/66 ,  H01L27/088 ,  H01L23/532 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/165

Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a plurality of conductive interconnect lines in and spaced apart by an inter-layer dielectric (ILD) layer above a substrate. Individual ones of the plurality of conductive interconnect lines have an upper surface below an upper surface of the ILD layer. An etch-stop layer is on and conformal with the ILD layer and the plurality of conductive interconnect lines, the etch-stop layer having a non-planar upper surface with an uppermost portion of the non-planar upper surface over the ILD layer and a lowermost portion of the non-planar upper surface over the plurality of conductive interconnect lines.

公开(公告)号：US11322504B2

公开(公告)日：2022-05-03

申请号：US16021019

申请日：2018-06-28

Applicant: Intel Corporation

Inventor： Uygar Avci ,  Daniel Morris ,  Seiyon Kim ,  Yih Wang ,  Ruth Brain ,  Ian Young

IPC: H01L27/11502 ,  H01L27/11 ,  H01L23/528 ,  H01L23/522 ,  H01L49/02 ,  H01L21/768 ,  H01L21/311

Abstract: Embodiments include a memory array and a method of forming the memory array. A memory array includes a first dielectric over first metal traces, where first metal traces extend along a first direction, second metal traces on the first dielectric, where second metal traces extend along a second direction perpendicular to the first direction, and third metal traces on the second dielectric, where third metal traces extend along the first direction. The memory array includes a ferroelectric capacitor positioned in a trench having sidewalls and bottom surface, where the trench has a depth defined from a top surface of first metal trace to the top surface of third metal trace. The memory array further includes an insulating sidewall, a first electrode, a ferroelectric, and a second electrode disposed in the trench, where the trench has a rectangular cylinder shape defined by the first, second, and third metal traces.