Invention Grant
- Patent Title: Layout design system and layout design method
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Application No.: US16622054Application Date: 2018-06-14
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Publication No.: US10949595B2Publication Date: 2021-03-16
- Inventor: Naoaki Tsutsui , Yusuke Koumura , Yuji Iwaki , Shunpei Yamazaki
- Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
- Applicant Address: JP Atsugi
- Assignee: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
- Current Assignee: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
- Current Assignee Address: JP Atsugi
- Agency: Fish & Richardson P.C.
- Priority: JPJP2017-122541 20170622
- International Application: PCT/IB2018/054348 WO 20180614
- International Announcement: WO2018/234945 WO 20181227
- Main IPC: G06F30/392
- IPC: G06F30/392 ; G06N3/08 ; G06N3/04 ; G06F30/27

Abstract:
A system performs a layout design of a circuit for a small area satisfying a design rule within a short period of time. In a layout design system which includes a processing portion and in which a circuit diagram and layout design information are input to the processing portion, the processing portion has a function of generating layout data from the circuit diagram and the layout design information by performing a Q learning, the processing portion has a function of outputting the layout data, the processing portion includes a first neural network, and the first neural network estimates an action value function in the Q learning.
Public/Granted literature
- US20200184137A1 LAYOUT DESIGN SYSTEM AND LAYOUT DESIGN METHOD Public/Granted day:2020-06-11
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