- 专利标题： Integer boundary spur mitigation for fractional PLL frequency synthesizers
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申请号： US16868547申请日： 2020-05-07
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公开(公告)号： US10965295B1公开(公告)日： 2021-03-30
- 发明人: Faisal Hussien , Ahmed Emira , Esmail Babakrpur Nalousi
- 申请人： GOODIX TECHNOLOGY INC.
- 申请人地址： US CA San Diego
- 专利权人： GOODIX TECHNOLOGY INC.
- 当前专利权人： GOODIX TECHNOLOGY INC.
- 当前专利权人地址： US CA San Diego
- 代理机构： Kilpatrick Townsend & Stockton LLP
- 主分类号： H03L7/07
- IPC分类号： H03L7/07 ; H04L7/033 ; H03L7/197 ; H04B1/04 ; H04B1/16
摘要：
A clock generation circuit is disclosed. The clock generation circuit includes a first PLL circuit configured to generate a first output clock based on a first input clock, where the first PLL circuit includes a first feedback divider circuit. The clock generation circuit also includes a second PLL circuit configured to generate a second output clock based on a second input clock, where the second PLL circuit includes a second feedback divider circuit. The first input clock is generated based on the second output clock.
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