A display apparatus includes a pixel array, a plurality of gate lines and a plurality of de-load lines. The pixel array includes a plurality of display rows, each of the display rows includes a plurality of pixel circuits, and each of the pixel circuits includes a first transistor and a second transistor coupled in series between a data line and a display pixel. A control end of the first transistor of each of the pixel circuits is coupled to one of the gate lines for receiving a gate driving signal. A control end of the second transistor of each of the pixel circuits is coupled to one of the de-load lines for receiving a de-loading signal. Where an enable time period of the de-loading signal received by each of the pixel circuits covers an enable time period of the gate driving signal received by each of the pixel circuits.