公开(公告)号：US10930239B2

公开(公告)日：2021-02-23

申请号：US16690606

申请日：2019-11-21

Applicant: AU Optronics Corporation

Inventor： Kai-Wei Hong ,  Chun-Da Tu ,  Ming-Hsien Lee ,  Chuang-Cheng Yang ,  Yi-Cheng Lin ,  Chun-Feng Lin

IPC: G11C19/00 ,  G09G3/36 ,  G11C19/28 ,  G09G3/20

Abstract: The present embodiment of the invention provides a gate driving circuit and a display apparatus using the gate driving circuit. The gate driving circuit has a plurality of shift registers, and each shift register includes a first output unit, a first pull-down unit, a second output unit, a second pull-down unit, a voltage coupling unit, and a voltage boosting unit. The first output unit is coupled to a node and a first output end. The second output unit is coupled to the node and a second output end. The first pull-down unit is coupled to the first output end and a reference potential. The second pull-down unit is coupled to the second output end and the reference potential. The voltage coupling unit is coupled between the node and the second output end. The voltage boosting unit is coupled to a preset potential, the first output end, and a node and a gate high potential of a shift register at a previous stage.

公开(公告)号：US10522105B2

公开(公告)日：2019-12-31

申请号：US15953720

申请日：2018-04-16

Applicant: AU Optronics Corporation

Inventor： Kai-Wei Hong ,  Chun-Da Tu ,  Ming-Hsien Lee ,  Chuang-Cheng Yang ,  Yi-Cheng Lin ,  Chun-Feng Lin

IPC: G11C19/00 ,  G09G3/36 ,  G11C19/28 ,  G09G3/20

Abstract: The present embodiment of the invention provides a gate driving circuit and a display apparatus using the gate driving circuit. The gate driving circuit has a plurality of shift registers, and each shift register includes a first output unit, a first pull-down unit, a second output unit, a second pull-down unit, a voltage coupling unit, and a voltage boosting unit. The first output unit is coupled to a node and a first output end. The second output unit is coupled to the node and a second output end. The first pull-down unit is coupled to the first output end and a reference potential. The second pull-down unit is coupled to the second output end and the reference potential. The voltage coupling unit is coupled between the node and the second output end. The voltage boosting unit is coupled to a preset potential, the first output end, and a node and a gate high potential of a shift register at a previous stage.

公开(公告)号：US20190064978A1

公开(公告)日：2019-02-28

申请号：US16008039

申请日：2018-06-14

Applicant: Au Optronics Corporation

Inventor： Chun-Da Tu ,  Ming-Hsien Lee ,  Kai-Wei Hong ,  Chuang-Cheng Yang ,  Yi-Cheng Lin ,  Chun-Feng Lin

IPC: G06F3/041 ,  G11C19/28 ,  G09G3/20

Abstract: A shift register and a touch display apparatus thereof are provided. The shift register includes a voltage setting unit, a driving unit, a control unit, a discharge unit, a first compensation transistor, and a second compensation transistor. The voltage setting unit sets a terminal voltage of an internal terminal. The driving unit is coupled to the internal terminal to provide a gate signal and a driving signal. The control unit receives the terminal voltage to provide a control signal. The discharge unit discharges the terminal voltage and the gate signal according to the control signal. The first compensation transistor and the second compensation transistor are coupled in series between a touch enable signal and the internal terminal, and control terminals of the first compensation transistor and the second compensation transistor receive the terminal voltage and the touch enable signal, respectively.

公开(公告)号：US10714668B2

公开(公告)日：2020-07-14

申请号：US16278731

申请日：2019-02-19

Applicant: Au Optronics Corporation

Inventor： Ming-Hsien Lee ,  Yi-Cheng Lin ,  Chuang-Cheng Yang ,  Kai-Wei Hong ,  Chun-Feng Lin

IPC: H01L25/075 ,  H01L33/62 ,  H01L27/12

Abstract: A light-emitting device includes a substrate, a circuit array including a plurality of circuit units disposed on the substrate, a first conductive pattern, a second conductive pattern, a first wire pattern, and a second wire pattern disposed on the circuit array, and a light-emitting element disposed on one of the circuit units. The light-emitting element includes a first electrode and a second electrode respectively electrically connected to the first conductive pattern and the second conductive pattern. The second electrode is not overlapped with the first wire pattern and the second wire pattern. A manufacturing method of the light-emitting device is also provided.

公开(公告)号：US20200028044A1

公开(公告)日：2020-01-23

申请号：US16278731

申请日：2019-02-19

Applicant: Au Optronics Corporation

Inventor： Ming-Hsien Lee ,  Yi-Cheng Lin ,  Chuang-Cheng Yang ,  Kai-Wei Hong ,  Chun-Feng Lin

IPC: H01L33/62 ,  H01L25/075 ,  H01L27/12

Abstract: A light-emitting device includes a substrate, a circuit array including a plurality of circuit units disposed on the substrate, a first conductive pattern, a second conductive pattern, a first wire pattern, and a second wire pattern disposed on the circuit array, and a light-emitting element disposed on one of the circuit units. The light-emitting element includes a first electrode and a second electrode respectively electrically connected to the first conductive pattern and the second conductive pattern. The second electrode is not overlapped with the first wire pattern and the second wire pattern. A manufacturing method of the light-emitting device is also provided.

公开(公告)号：US09640554B2

公开(公告)日：2017-05-02

申请号：US14468349

申请日：2014-08-26

Applicant: Au Optronics Corporation

Inventor： Yi-Cheng Lin ,  Yu-Chi Chen

IPC: H01L27/12 ,  H01L33/38 ,  H01L27/32

CPC classification number: H01L27/1225 ,  H01L27/124 ,  H01L27/1255 ,  H01L27/3244 ,  H01L33/387 ,  H01L2227/323

Abstract: A pixel structure includes a semiconductor layer, an insulating layer, a first conductive layer, a second conductive layer, a passivation layer, and a first electrode layer. The semiconductor layer includes a first semiconductor pattern having a first source region, a first drain region, and a first channel region. The insulating layer is disposed on the semiconductor layer. The first conductive layer is disposed on the insulating layer and includes a first gate, a first source, a first drain, and a data line connected to the first source. The second conductive layer is disposed on the first conductive layer and includes a scan line. The passivation layer covers the first and second conductive layers and the semiconductor layer. The first electrode layer is disposed on the passivation layer and provides electrical connection to different layers.

公开(公告)号：US09214476B1

公开(公告)日：2015-12-15

申请号：US14468353

申请日：2014-08-26

Applicant: Au Optronics Corporation

Inventor： Yi-Cheng Lin ,  Yu-Chi Chen

IPC: H01L27/12 ,  H01L33/38 ,  H01L27/32

CPC classification number: H01L27/1225 ,  H01L27/124 ,  H01L27/1255 ,  H01L27/3244 ,  H01L27/3258 ,  H01L27/326 ,  H01L27/3262 ,  H01L27/3265 ,  H01L27/3276 ,  H01L33/387 ,  H01L51/5218 ,  H01L2251/308

Abstract: A pixel structure includes a first conductive layer, a semiconductor layer, an insulating layer, a second conductive layer, a passivation layer, and a first electrode layer. The first conductive layer includes a scan line and a bottom electrode. The semiconductor layer includes a first semiconductor pattern having a first source region, a first drain region, and a first channel region. The insulating layer is disposed on the semiconductor layer. The second conductive layer is disposed on the insulating layer and includes a top electrode, a first gate, a first source, a first drain, and a data line connected with the first source. The bottom electrode and the top electrode overlap to form a capacitor. The passivation layer covers the first and second conductive layers and the semiconductor layer. The first electrode layer is disposed on the passivation layer and provides electrical connection to different layers.

Abstract translation: 像素结构包括第一导电层，半导体层，绝缘层，第二导电层，钝化层和第一电极层。 第一导电层包括扫描线和底部电极。 半导体层包括具有第一源极区，第一漏极区和第一沟道区的第一半导体图案。 绝缘层设置在半导体层上。 第二导电层设置在绝缘层上，包括顶电极，第一栅极，第一源极，第一漏极和与第一源极连接的数据线。 底部电极和顶部电极重叠以形成电容器。 钝化层覆盖第一和第二导电层和半导体层。 第一电极层设置在钝化层上并提供与不同层的电连接。

公开(公告)号：US10971045B2

公开(公告)日：2021-04-06

申请号：US16441018

申请日：2019-06-14

Applicant: Au Optronics Corporation

Inventor： Chun-Feng Lin ,  Chuang-Cheng Yang ,  Ming-Hsien Lee ,  Yi-Cheng Lin ,  Wei-Chia Chiu

IPC: G09G3/20

Abstract: A display apparatus includes a pixel array, a plurality of gate lines and a plurality of de-load lines. The pixel array includes a plurality of display rows, each of the display rows includes a plurality of pixel circuits, and each of the pixel circuits includes a first transistor and a second transistor coupled in series between a data line and a display pixel. A control end of the first transistor of each of the pixel circuits is coupled to one of the gate lines for receiving a gate driving signal. A control end of the second transistor of each of the pixel circuits is coupled to one of the de-load lines for receiving a de-loading signal. Where an enable time period of the de-loading signal received by each of the pixel circuits covers an enable time period of the gate driving signal received by each of the pixel circuits.

公开(公告)号：US20200211433A1

公开(公告)日：2020-07-02

申请号：US16441018

申请日：2019-06-14

Applicant: Au Optronics Corporation

Inventor： Chun-Feng Lin ,  Chuang-Cheng Yang ,  Ming-Hsien Lee ,  Yi-Cheng Lin ,  Wei-Chia Chiu

IPC: G09G3/20

Abstract: A display apparatus includes a pixel array, a plurality of gate lines and a plurality of de-load lines. The pixel array includes a plurality of display rows, each of the display rows includes a plurality of pixel circuits, and each of the pixel circuits includes a first transistor and a second transistor coupled in series between a data line and a display pixel. A control end of the first transistor of each of the pixel circuits is coupled to one of the gate lines for receiving a gate driving signal. A control end of the second transistor of each of the pixel circuits is coupled to one of the de-load lines for receiving a de-loading signal. Where an enable time period of the de-loading signal received by each of the pixel circuits covers an enable time period of the gate driving signal received by each of the pixel circuits.

公开(公告)号：US20150340383A1

公开(公告)日：2015-11-26

申请号：US14468349

申请日：2014-08-26

Applicant: Au Optronics Corporation

Inventor： Yi-Cheng Lin ,  Yu-Chi Chen

IPC: H01L27/12 ,  H01L33/38

CPC classification number: H01L27/1225 ,  H01L27/124 ,  H01L27/1255 ,  H01L27/3244 ,  H01L33/387 ,  H01L2227/323

Abstract: A pixel structure includes a semiconductor layer, an insulating layer, a first conductive layer, a second conductive layer, a passivation layer, and a first electrode layer. The semiconductor layer includes a first semiconductor pattern having a first source region, a first drain region, and a first channel region. The insulating layer is disposed on the semiconductor layer. The first conductive layer is disposed on the insulating layer and includes a first gate, a first source, a first drain, and a data line connected to the first source. The second conductive layer is disposed on the first conductive layer and includes a scan line. The passivation layer covers the first and second conductive layers and the semiconductor layer. The first electrode layer is disposed on the passivation layer and provides electrical connection to different layers.

Abstract translation: 像素结构包括半导体层，绝缘层，第一导电层，第二导电层，钝化层和第一电极层。 半导体层包括具有第一源极区，第一漏极区和第一沟道区的第一半导体图案。 绝缘层设置在半导体层上。 第一导电层设置在绝缘层上，并且包括第一栅极，第一源极，第一漏极和连接到第一源极的数据线。 第二导电层设置在第一导电层上并且包括扫描线。 钝化层覆盖第一和第二导电层和半导体层。 第一电极层设置在钝化层上并提供与不同层的电连接。