Invention Grant
- Patent Title: Method of manufacturing SiC epitaxial wafer
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Application No.: US16672650Application Date: 2019-11-04
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Publication No.: US10985079B2Publication Date: 2021-04-20
- Inventor: Yoshitaka Nishihara
- Applicant: SHOWA DENKO K.K.
- Applicant Address: JP Tokyo
- Assignee: SHOWA DENKO K.K.
- Current Assignee: SHOWA DENKO K.K.
- Current Assignee Address: JP Tokyo
- Agency: Sughrue Mion, PLLC
- Priority: JPJP2018-211273 20181109
- Main IPC: H01L21/66
- IPC: H01L21/66 ; H01L21/02

Abstract:
The invention provides a method of manufacturing a SiC epitaxial wafer in which stacking faults are less likely to occur when a current is passed in a forward direction. The method of manufacturing the SiC epitaxial wafer includes a measurement step for measuring a basal plane dislocation density, a layer structure determining process for determining the layer structure of the epitaxial layer, and an epitaxial growth step for growing the epitaxial layers. And in the layer structure determination step, in the case of (i) when the basal plane dislocation density is lower than a predetermined value, the epitaxial layer includes a conversion layer and a drift layer from the SiC substrate side; and in the case of (ii) when the density is equal to or higher than the predetermined value, the epitaxial layer includes a conversion layer, a recombination layer, and a drift layer from the SiC substrate side.
Public/Granted literature
- US20200152528A1 METHOD OF MANUFACTURING SIC EPITAXIAL WAFER Public/Granted day:2020-05-14
Information query
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