Invention Grant
- Patent Title: Method for biasing a differential pair of transistors, and corresponding integrated circuit
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Application No.: US16885737Application Date: 2020-05-28
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Publication No.: US10985750B2Publication Date: 2021-04-20
- Inventor: Yohan Joly , Vincent Binet , Michel Cuenca
- Applicant: STMicroelectronics (Rousset) SAS
- Applicant Address: FR Rousset
- Assignee: STMicroelectronics (Rousset) SAS
- Current Assignee: STMicroelectronics (Rousset) SAS
- Current Assignee Address: FR Rousset
- Agency: Slater Matsil, LLP
- Priority: FR1906167 20190611
- Main IPC: H03K17/56
- IPC: H03K17/56 ; H03F3/45

Abstract:
An integrated circuit includes at least one differential pair of transistors, a bias current generator that is configured to generate a bias current on a bias node that is coupled to a source terminal of each transistor of said differential pair by a respective resistive element. A compensation current generator is configured to generate a compensation current in one of the two resistive elements so as to compensate for a difference between actual values of the threshold voltages of the transistors of said differential pair.
Public/Granted literature
- US2153649A Car truck Public/Granted day:1939-04-11
Information query
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