公开(公告)号：US11031917B2

公开(公告)日：2021-06-08

申请号：US16425437

申请日：2019-05-29

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Vincent Binet ,  Yohan Joly

IPC: H03F3/45

Abstract: An operational amplifier integrated circuit includes a differential pair of transistors having a first input, a second input. A bias current generator applies a bias current to an output of the differential pair of transistors. A control loop generates a control voltage arising from a difference in potentials between the first input and the second input. An additional current that is added to the bias current is generated in response to the control voltage.

公开(公告)号：US10985750B2

公开(公告)日：2021-04-20

申请号：US16885737

申请日：2020-05-28

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Yohan Joly ,  Vincent Binet ,  Michel Cuenca

IPC: H03K17/56 ,  H03F3/45

Abstract: An integrated circuit includes at least one differential pair of transistors, a bias current generator that is configured to generate a bias current on a bias node that is coupled to a source terminal of each transistor of said differential pair by a respective resistive element. A compensation current generator is configured to generate a compensation current in one of the two resistive elements so as to compensate for a difference between actual values of the threshold voltages of the transistors of said differential pair.

公开(公告)号：US09460808B2

公开(公告)日：2016-10-04

申请号：US14549291

申请日：2014-11-20

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Bruno Gailhard ,  Yohan Joly

IPC: H03K5/00 ,  G11C27/02 ,  G11C29/50 ,  G11C29/02 ,  H03K3/0231

CPC classification number: G11C27/024 ,  G11C29/023 ,  G11C29/028 ,  G11C29/50016 ,  H03K3/0231

Abstract: A method is provided for controlling a sample and hold circuit that includes a switching module coupled to a storage capacitor. A circuit external to the sample and hold circuit of generates at least one main current representative of at least one leakage current of the switching module in its off state. The at least one main current is delivered to at least one auxiliary capacitor. An initial pulse signal is generated from the charging and discharging of the at least one auxiliary capacitor. The sampling phase of the sample and hold circuit is triggered at the rate of the pulses of a pulse signal derived from the initial pulse signal.

Abstract translation: 提供了一种用于控制采样和保持电路的方法，该采样和保持电路包括耦合到存储电容器的开关模块。 采样和保持电路外部的电路产生代表切换模块处于其关闭状态的至少一个泄漏电流的至少一个主电流。 至少一个主电流被传送到至少一个辅助电容器。 从至少一个辅助电容器的充电和放电产生初始脉冲信号。 采样和保持电路的采样相位以从初始脉冲信号得到的脉冲信号脉冲的速率被触发。

公开(公告)号：US20200014376A1

公开(公告)日：2020-01-09

申请号：US16449700

申请日：2019-06-24

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Yohan Joly ,  Vincent Binet

IPC: H03K5/24 ,  H03F3/45 ,  H03K3/3565

Abstract: A comparator includes a folded cascode stage having positive and negative outputs. The folded cascode stage includes: a common-mode voltage regulation circuit that includes resistive elements that are respectively situated between each of the outputs and a common-mode node. A compensation circuit is configured to regulate a difference between the voltages on the outputs, and is configured to generate a constant and continuous compensation current in the two resistive elements. A hysteresis circuit is configured to offset voltages on the outputs, and to generate a hysteresis current in the two resistive elements.

公开(公告)号：US20150155053A1

公开(公告)日：2015-06-04

申请号：US14549291

申请日：2014-11-20

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Bruno Gailhard ,  Yohan Joly

IPC: G11C27/02

CPC classification number: G11C27/024 ,  G11C29/023 ,  G11C29/028 ,  G11C29/50016 ,  H03K3/0231

Abstract: A method is provided for controlling a sample and hold circuit that includes a switching module coupled to a storage capacitor. A circuit external to the sample and hold circuit of generates at least one main current representative of at least one leakage current of the switching module in its off state. The at least one main current is delivered to at least one auxiliary capacitor. An initial pulse signal is generated from the charging and discharging of the at least one auxiliary capacitor. The sampling phase of the sample and hold circuit is triggered at the rate of the pulses of a pulse signal derived from the initial pulse signal.

Abstract translation: 提供了一种用于控制采样和保持电路的方法，该采样和保持电路包括耦合到存储电容器的开关模块。 采样和保持电路外部的电路产生代表切换模块处于其关闭状态的至少一个泄漏电流的至少一个主电流。 至少一个主电流被传送到至少一个辅助电容器。 从至少一个辅助电容器的充电和放电产生初始脉冲信号。 采样和保持电路的采样相位以从初始脉冲信号得到的脉冲信号脉冲的速率被触发。