A circuit comprising a first processing element having a first output configured to couple to a voltage control circuit, a second output configured to couple to a gate terminal of a first transistor, and a third output configured to couple to a first node and a control circuit. The control circuit comprises a second processing element having multiple outputs, a second transistor having a gate terminal configured to couple to one of the outputs of the second processing element, a first terminal configured to couple to a second node and to a drain terminal of the first transistor, and a second terminal, and a third transistor having a gate terminal configured to couple to a second of the outputs of the second processing element, a first terminal configured to couple to a third node, and a second terminal.