A memory in-pixel (MIP) circuit, a driving method of the MIP circuit, and an LCD panel fabricated using the MIP circuit. The MIP circuit comprising an input circuit, a control circuit and an output circuit. The input circuit brings the first input terminal and the second input terminal into conduction with a first node and a second node respectively in response to the first control signal of the first control terminal being active. The control circuit is configured to set and maintain the potential of a third node or a fourth node active based on the potential of the first node and the second node. The output circuit is configured to bring the output terminal into conduction with the first or second input terminal according to the potential of the third and the fourth node in response to the second control signal of the second control terminal being active.