Invention Grant
- Patent Title: Ultra low parasitic inductance integrated cascode GaN devices
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Application No.: US16355008Application Date: 2019-03-15
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Publication No.: US10991722B2Publication Date: 2021-04-27
- Inventor: Ko-Tao Lee , Xin Zhang , Todd E. Takken
- Applicant: International Business Machines Corporation
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agency: Scully, Scott, Murphy & Presser, P.C.
- Agent L. Jeffrey Kelly, Esq.
- Main IPC: H01L27/12
- IPC: H01L27/12 ; H01L29/78 ; H01L21/84 ; H01L29/04 ; H01L29/778

Abstract:
One silicon MOSFET transistor, which is used as the VThreshold control, and a GaN power HEMT are integrated on a single die to enable a fully integrated depletion-mode power device. GaN area is created on a silicon substrate and GaN FETs are built in the GaN area. Outside of the GaN area, silicon transistors such as switch MOSFETs are built. Front end of line or back end of line metal connections are then made to create interconnections among the GaN FET and the silicon transistor. The short physical proximity of the silicon transistor and GaN HEMT significantly reduces the parasitic resistance and inductance between them. Thus, high speed signals are able to travel from the silicon transistor to the GaN HEMT with a higher frequency and lower distortion, without creating overshoot voltage when there is large parasitic inductance. Therefore, the cascode device can operate at a higher switching frequency.
Public/Granted literature
- US20200295045A1 ULTRA LOW PARASITIC INDUCTANCE INTEGRATED CASCODE GaN DEVICES Public/Granted day:2020-09-17
Information query
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