Invention Grant
- Patent Title: Zero padding apparatus for encoding fixed-length signaling information and zero padding method using same
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Application No.: US16390316Application Date: 2019-04-22
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Publication No.: US10992316B2Publication Date: 2021-04-27
- Inventor: Sung-Ik Park , Sun-Hyoung Kwon , Jae-Young Lee , Heung-Mook Kim
- Applicant: Electronics and Telecommunications Research Institute
- Applicant Address: KR Daejeon
- Assignee: Electronics and Telecommunications Research Institute
- Current Assignee: Electronics and Telecommunications Research Institute
- Current Assignee Address: KR Daejeon
- Agency: NSIP Law
- Priority: KR10-2015-0028060 20150227,KR10-2015-0031947 20150306,KR10-2016-0020636 20160222
- Main IPC: G06F11/00
- IPC: G06F11/00 ; H03M13/00 ; H03M13/11 ; H03M13/25 ; H03M13/27 ; H03M13/29 ; H03M13/15 ; G06T7/162 ; H04W72/04

Abstract:
A zero padding apparatus and method for fixed length signaling information are disclosed. A zero padding apparatus according to an embodiment of the present invention includes a processor configured to generate a LDPC information bit string by deciding a number of groups whose all bits are to be filled with 0 using a difference between a length of the LDPC information bit string and a length of a BCH-encoded bit string, selecting the groups using a shortening pattern order to fill all the bits of the groups with 0, and filling at least a part of remaining groups, which are not filled with 0, with the BCH-encoded bit string; and memory configured to provide the LDPC information bit string to an LDPC encoder.
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