- 专利标题： Vertical transistor having reduced edge fin variation
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申请号： US16284261申请日： 2019-02-25
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公开(公告)号： US11004751B2公开(公告)日： 2021-05-11
- 发明人: Kangguo Cheng , Juntao Li , Dexin Kong , Zhenxing Bi
- 申请人： International Business Machines Corporation
- 申请人地址： US NY Armonk
- 专利权人： International Business Machines Corporation
- 当前专利权人： International Business Machines Corporation
- 当前专利权人地址： US NY Armonk
- 代理机构： Cantor Colburn LLP
- 代理商 Douglas Pearson
- 主分类号： H01L21/8234
- IPC分类号： H01L21/8234 ; H01L21/762 ; H01L29/66 ; H01L27/088 ; H01L21/311 ; H01L29/06 ; H01L21/308 ; H01L21/3065
摘要：
A semiconductor device includes a substrate with a first semiconductor fin and a second semiconductor fin formed thereon. A pair of opposing dielectric trench spacers are between the first and second semiconductor fins. The opposing dielectric trench spacers define an isolation region therebetween. The semiconductor device further includes a shallow trench isolation (STI) element formed in the isolation region. The STI element includes a lower portion on the substrate and an upper portion located opposite the lower portion. The upper portion extends above an upper end of the dielectric trench spacers.
公开/授权文献
- US20200273756A1 VERTICAL TRANSISTOR HAVING REDUCED EDGE FIN VARIATION 公开/授权日：2020-08-27
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