Invention Grant
- Patent Title: Vertical transistor having reduced edge fin variation
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Application No.: US16284261Application Date: 2019-02-25
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Publication No.: US11004751B2Publication Date: 2021-05-11
- Inventor: Kangguo Cheng , Juntao Li , Dexin Kong , Zhenxing Bi
- Applicant: International Business Machines Corporation
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agency: Cantor Colburn LLP
- Agent Douglas Pearson
- Main IPC: H01L21/8234
- IPC: H01L21/8234 ; H01L21/762 ; H01L29/66 ; H01L27/088 ; H01L21/311 ; H01L29/06 ; H01L21/308 ; H01L21/3065

Abstract:
A semiconductor device includes a substrate with a first semiconductor fin and a second semiconductor fin formed thereon. A pair of opposing dielectric trench spacers are between the first and second semiconductor fins. The opposing dielectric trench spacers define an isolation region therebetween. The semiconductor device further includes a shallow trench isolation (STI) element formed in the isolation region. The STI element includes a lower portion on the substrate and an upper portion located opposite the lower portion. The upper portion extends above an upper end of the dielectric trench spacers.
Public/Granted literature
- US20200273756A1 VERTICAL TRANSISTOR HAVING REDUCED EDGE FIN VARIATION Public/Granted day:2020-08-27
Information query
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