Invention Grant
- Patent Title: Semiconductor device structure having a plurality of threshold voltages and method of forming the same
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Application No.: US16656744Application Date: 2019-10-18
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Publication No.: US11018257B2Publication Date: 2021-05-25
- Inventor: Yu-San Chien , Hsin-Che Chiang , Chun-Sheng Liang , Kuo-Hua Pan
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsinchu
- Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee Address: TW Hsinchu
- Agency: Haynes and Boone, LLP
- Main IPC: H01L21/225
- IPC: H01L21/225 ; H01L29/78 ; H01L29/66 ; H01L27/092 ; H01L21/8238 ; H01L21/768 ; H01L21/02

Abstract:
An embodiment method includes forming a semiconductor liner layer on a first fin structure and on a second fin structure and forming a first capping layer on the semiconductor liner layer disposed on the first fin structure. The method further includes forming a second capping layer on the semiconductor liner layer disposed on the first fin structure, where a composition of the first capping layer is different from a composition of the second capping layer. The method additionally includes performing a thermal process on the first capping layer, the second capping layer, and the semiconductor liner layer to form a first channel region in the first fin structure and a second channel region in the second fin structure. A concentration profile of a material of the first channel region is different from a concentration profile of a material of the second channel region.
Public/Granted literature
- US20210119033A1 Semiconductor Device Structure Having a Plurality of Threshold Voltages and Method of Forming the Same Public/Granted day:2021-04-22
Information query
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