公开(公告)号：US20240363731A1

公开(公告)日：2024-10-31

申请号：US18768952

申请日：2024-07-10

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Wei-Chih Kao ,  Hsin-Che Chiang ,  Yu-San Chien ,  Chun-Sheng Liang ,  Kuo-Hua Pan

IPC分类号： H01L29/66 ,  H01L21/033 ,  H01L21/324 ,  H01L21/762 ,  H01L21/768 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/78

CPC分类号： H01L29/66795 ,  H01L21/0337 ,  H01L21/324 ,  H01L21/762 ,  H01L21/76832 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823878 ,  H01L27/0922 ,  H01L29/0649 ,  H01L29/66545 ,  H01L29/785

摘要： An embodiment method includes: forming a semiconductor liner layer on exposed surfaces of a fin structure that extends above a dielectric isolation structure disposed over a substrate; forming a first capping layer to laterally surround a bottom portion of the semiconductor liner layer; forming a second capping layer over an upper portion of the semiconductor liner layer; and annealing the fin structure having the semiconductor liner layer, the first capping layer, and the second capping layer thereon, the annealing driving a dopant from the semiconductor liner layer into the fin structure, wherein a dopant concentration profile in a bottom portion of the fin structure is different from a dopant concentration profile in an upper portion of the fin structure.

公开(公告)号：US20240014077A1

公开(公告)日：2024-01-11

申请号：US18150642

申请日：2023-01-05

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Bo-Cyuan Lu ,  Hsin-Che Chiang ,  Tai-Chun Huang ,  Chi On Chui

IPC分类号： H01L21/8238 ,  H01L27/092

CPC分类号： H01L21/823878 ,  H01L27/0924 ,  H01L21/823821

摘要： A method includes forming a gate stack on a semiconductor region, etching the gate stack to form a first trench separating the gate stack into a first gate stack portion and a second gate stack portion, and forming a gate isolation region filling the first trench. The gate isolation region includes a silicon nitride liner, and a silicon oxide filling-region overlapping a first bottom portion of the silicon nitride liner. The method further includes etching the gate stack to form a second trench and to reveal a protruding semiconductor fin, and etching the protruding semiconductor fin to extend the second trench into the bulk semiconductor substrate. A fin isolation region is formed to fill the second trench. The fin isolation region includes a silicon oxide liner, and a silicon nitride filling-region overlapping a second bottom portion of the silicon oxide liner.

公开(公告)号：US20230378360A1

公开(公告)日：2023-11-23

申请号：US18361514

申请日：2023-07-28

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Ju-Li Huang ,  Hsin-Che Chiang ,  Yu-Chi Pan ,  Chun-Ming Yang ,  Chun-Sheng Liang ,  Ying-Liang Chuang ,  Ming-Hsi Yeh

IPC分类号： H01L29/78 ,  H01L29/423 ,  H01L21/285 ,  H01L29/40 ,  H01L21/3213 ,  H01L29/49

CPC分类号： H01L29/785 ,  H01L29/42372 ,  H01L21/28556 ,  H01L29/401 ,  H01L21/32134 ,  H01L29/4966

摘要： The present disclosure describes structure and method of a fin field-effect transistor (finFET) device. The finFET device includes: a substrate, a fin over the substrate, and a gate structure over the fin. The gate structure includes a work-function metal (WFM) layer over an inner sidewall of the gate structure. A topmost surface of the WFM layer is lower than a top surface of the gate structure. The gate structure also includes a filler gate metal layer over the topmost surface of the WFM layer. A top surface of the filler gate metal layer is substantially co-planar with the top surface of the gate structure. The gate structure further includes a self-assembled monolayer (SAM) between the filler gate metal layer and the WFM layer.

公开(公告)号：US11670697B2

公开(公告)日：2023-06-06

申请号：US17353606

申请日：2021-06-21

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Hsin-Che Chiang ,  Ju-Yuan Tzeng ,  Chun-Sheng Liang ,  Chih-Yang Yeh ,  Shu-Hui Wang ,  Jeng-Ya David Yeh

IPC分类号： H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/49 ,  H01L21/28 ,  H01L21/768 ,  H01L23/528 ,  H01L23/532 ,  H01L29/165 ,  H01L29/51

CPC分类号： H01L29/42372 ,  H01L21/28088 ,  H01L21/7684 ,  H01L21/76846 ,  H01L23/5283 ,  H01L23/5329 ,  H01L23/53204 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7851 ,  H01L29/165 ,  H01L29/517 ,  H01L29/7843 ,  H01L29/7848

摘要： A semiconductor device includes a substrate comprising a semiconductor fin, a gate structure over the semiconductor fin, and source/drain structures over the semiconductor fin and on opposite sides of the gate structure. The gate stack comprises a high-k dielectric layer; a first work function metal layer over the high-k dielectric layer; an oxide of the first work function metal layer over the first work function metal layer; and a second work function metal layer over the oxide of the first work function metal layer, in which the first and second work function metal layers have different compositions; and a gate electrode over the second work function metal layer.

公开(公告)号：US11145730B2

公开(公告)日：2021-10-12

申请号：US16678642

申请日：2019-11-08

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Hsin-Che Chiang ,  Ju-Yuan Tzeng ,  Chun-Sheng Liang ,  Shu-Hui Wang ,  Chih-Yang Yeh ,  Jeng-Ya David Yeh

IPC分类号： H01L27/092 ,  H01L29/423 ,  H01L29/49 ,  H01L27/088 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/3213 ,  H01L21/8238 ,  H01L29/40 ,  H01L29/51 ,  H01L29/417 ,  H01L29/43 ,  H01L29/78 ,  H01L29/165

摘要： A semiconductor device includes a substrate, a first gate structure, a plurality of first gate spacers, a second gate structure, and a plurality of second gate spacers. The substrate has a first fin structure and a second fin structure. The first gate structure is over the first fin structure, in which the first gate structure includes a first high dielectric constant material and a first metal. A bottom surface of the first high dielectric constant material is higher than bottom surfaces of the first gate spacers. The second gate structure is narrower than the first gate structure and over the second fin structure, in which the second gate structure includes a second high dielectric constant material and a second metal. A bottom surface of the second high dielectric constant material is lower than bottom surfaces of the second gate spacers.

公开(公告)号：US20210082686A1

公开(公告)日：2021-03-18

申请号：US16573656

申请日：2019-09-17

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Hsin-Che Chiang ,  Wei-Chih Kao ,  Chun-Sheng Liang ,  Kuo-Hua Pan

IPC分类号： H01L21/02 ,  H01L29/66 ,  H01L29/78 ,  H01L29/08

摘要： A method includes providing a semiconductor substrate; epitaxially growing a blocking layer from a top surface of the semiconductor substrate, wherein the blocking layer has a lattice constant different from the semiconductor substrate; epitaxially growing a semiconductor layer above the blocking layer; patterning the semiconductor layer to form a semiconductor fin, wherein the blocking layer is under the semiconductor fin; forming a source/drain (S/D) feature in contact with the semiconductor fin; and forming a gate structure engaging the semiconductor fin.

公开(公告)号：US20200152772A1

公开(公告)日：2020-05-14

申请号：US16746097

申请日：2020-01-17

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Ju-Li Huang ,  Chun-Sheng Liang ,  Ming-Chi Huang ,  Ming-Hsi Yeh ,  Ying-Liang Chuang ,  Hsin-Che Chiang

IPC分类号： H01L29/66 ,  H01L21/8234 ,  H01L21/3213 ,  H01L21/311 ,  H01L29/78

摘要： Methods for, and structures formed by, wet process assisted approaches implemented in a replacement gate process are provided. Generally, in some examples, a wet etch process for removing a capping layer can form a first monolayer on the underlying layer as an adhesion layer and a second monolayer on, e.g., an interfacial dielectric layer between a gate spacer and a fin as an etch protection mechanism. Generally, in some examples, a wet process can form a monolayer on a metal layer, like a barrier layer of a work function tuning layer, as a hardmask for patterning of the metal layer.

公开(公告)号：US10541317B2

公开(公告)日：2020-01-21

申请号：US15909847

申请日：2018-03-01

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Ju-Li Huang ,  Chun-Sheng Liang ,  Ming-Chi Huang ,  Ming-Hsi Yeh ,  Ying-Liang Chuang ,  Hsin-Che Chiang

IPC分类号： H01L29/66 ,  H01L29/78 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/8234 ,  H01L21/321 ,  H01L21/3105 ,  H01L21/02 ,  H01L21/027

摘要： Methods for, and structures formed by, wet process assisted approaches implemented in a replacement gate process are provided. Generally, in some examples, a wet etch process for removing a capping layer can form a first monolayer on the underlying layer as an adhesion layer and a second monolayer on, e.g., an interfacial dielectric layer between a gate spacer and a fin as an etch protection mechanism. Generally, in some examples, a wet process can form a monolayer on a metal layer, like a barrier layer of a work function tuning layer, as a hardmask for patterning of the metal layer.

公开(公告)号：US10535653B2

公开(公告)日：2020-01-14

申请号：US15844593

申请日：2017-12-17

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Yi-Jen Chen ,  Chun-Sheng Liang ,  Shu-Hui Wang ,  Shih-Hsun Chang ,  Hsin-Che Chiang

IPC分类号： H01L27/088 ,  H01L29/06 ,  H01L29/49 ,  H01L29/51 ,  H01L29/423 ,  H01L21/8234 ,  H01L21/02 ,  H01L21/762 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/8238

摘要： A semiconductor structure includes a pair of gate structures and an isolation structure. Each of the gate structures includes a work function metal, a gate, and a barrier layer between the work function metal and the gate. The isolation structure is disposed between the gate structures. The barrier layer covers a sidewall of the isolation structure.

公开(公告)号：US12027415B2

公开(公告)日：2024-07-02

申请号：US17815177

申请日：2022-07-26

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Hsin-Che Chiang ,  Ju-Li Huang ,  Chun-Sheng Liang ,  Jeng-Ya Yeh

IPC分类号： H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L29/417 ,  H01L21/311

CPC分类号： H01L21/7682 ,  H01L21/76819 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76865 ,  H01L23/5226 ,  H01L23/5329 ,  H01L29/41775 ,  H01L21/31111 ,  H01L21/31116 ,  H01L23/53238 ,  H01L23/53252 ,  H01L23/53266

摘要： In one exemplary aspect, a method for semiconductor manufacturing comprises forming first and second silicon nitride features on sidewall surfaces of a contact hole, where the contact hole is disposed in a dielectric layer and above a source/drain (S/D) feature. The method further comprises forming a contact plug in the contact hole, the contact plug being electrically coupled to the S/D feature, removing a top portion of the contact plug to create a recess in the contact hole, forming a hard mask layer in the recess, and removing the first and second silicon nitride features via selective etching to form first and second air gaps, respectively.