Invention Grant
- Patent Title: 3D-interconnect
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Application No.: US16245925Application Date: 2019-01-11
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Publication No.: US11031362B2Publication Date: 2021-06-08
- Inventor: Chok J. Chia , Qwai H. Low , Patrick Variot
- Applicant: Invensas Corporation
- Applicant Address: US CA San Jose
- Assignee: Invensas Corporation
- Current Assignee: Invensas Corporation
- Current Assignee Address: US CA San Jose
- Agency: Lerner, David, Littenberg, Krumholz & Mentlik, LLP
- Main IPC: H01L21/56
- IPC: H01L21/56 ; H01L23/00 ; H01L21/52 ; H01L25/065 ; H01L23/538 ; H01L23/31 ; H01L25/10 ; H01L23/498

Abstract:
A method of making a microelectronic package includes bonding a conductive structure to a carrier. The conductive structure can include a base and a plurality of interconnections extending continuously away from the base toward the carrier. The microelectronic element can be positioned between at least two adjacent interconnections of the plurality of interconnections. The conductive structure may be bonded to the carrier so that the conductive structure overlies a rear surface of a microelectronic element disposed on the carrier and an exposed top surface of the carrier. The plurality of interconnections and the microelectronic element may be encapsulated. The carrier may be removed to expose free ends of the interconnections and bond pads of the microelectronic element. The free ends of the interconnections and bond pads of the microelectronic element may be conductively connected with terminals of the microelectronic package. The conductive structure may be patterned to form external contacts.
Public/Granted literature
- US20190148324A1 3D-Interconnect Public/Granted day:2019-05-16
Information query
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