公开(公告)号：US20180308813A1

公开(公告)日：2018-10-25

申请号：US15493917

申请日：2017-04-21

Applicant: Invensas Corporation

Inventor： Chok J. Chia ,  Qwai H. Low ,  Patrick Variot

IPC: H01L23/00 ,  H01L23/31 ,  H01L21/56 ,  H01L21/52 ,  H01L25/065 ,  H01L23/538

CPC classification number: H01L24/09 ,  H01L21/52 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/17 ,  H01L24/19 ,  H01L24/20 ,  H01L24/81 ,  H01L25/0652 ,  H01L2224/02331 ,  H01L2224/0401

Abstract: A method of making a microelectronic package includes bonding a conductive structure to a carrier so that the conductive structure overlies a rear surface of a microelectronic element disposed on the carrier and an exposed top surface of the carrier. The conductive structure may be a monolithic structure having a base and a plurality of interconnections extending continuously away from the base toward the carrier. The plurality of interconnections may have free ends that overlie the carrier. The microelectronic element may be positioned between at least two adjacent interconnections of the plurality of interconnections. The plurality of interconnections and the microelectronic element may be encapsulated with an encapsulant. The carrier may be removed to expose the free ends of the interconnections and bond pads of the microelectronic element. The free ends of the interconnections and the bond pads of the microelectronic element may be conductively connected with the terminals of the microelectronic package. The conductive structure may be patterned to form external contacts. At least some of the external contacts may overlie the microelectronic element.

公开(公告)号：US11031362B2

公开(公告)日：2021-06-08

申请号：US16245925

申请日：2019-01-11

Applicant: Invensas Corporation

Inventor： Chok J. Chia ,  Qwai H. Low ,  Patrick Variot

IPC: H01L21/56 ,  H01L23/00 ,  H01L21/52 ,  H01L25/065 ,  H01L23/538 ,  H01L23/31 ,  H01L25/10 ,  H01L23/498

Abstract: A method of making a microelectronic package includes bonding a conductive structure to a carrier. The conductive structure can include a base and a plurality of interconnections extending continuously away from the base toward the carrier. The microelectronic element can be positioned between at least two adjacent interconnections of the plurality of interconnections. The conductive structure may be bonded to the carrier so that the conductive structure overlies a rear surface of a microelectronic element disposed on the carrier and an exposed top surface of the carrier. The plurality of interconnections and the microelectronic element may be encapsulated. The carrier may be removed to expose free ends of the interconnections and bond pads of the microelectronic element. The free ends of the interconnections and bond pads of the microelectronic element may be conductively connected with terminals of the microelectronic package. The conductive structure may be patterned to form external contacts.

公开(公告)号：US20210366857A1

公开(公告)日：2021-11-25

申请号：US17340469

申请日：2021-06-07

Applicant: Invensas Corporation

Inventor： Chok J. Chia ,  Qwai H. Low ,  Patrick Variot

IPC: H01L23/00 ,  H01L21/56 ,  H01L21/52 ,  H01L25/065 ,  H01L23/538

Abstract: A microelectronic assembly comprises a microelectronic element, a redistribution structure, a plurality of backside conductive components and an encapsulant. The redistribution structure may be configured to conductively connect bond pads of the microelectronic element with terminals of the microelectronic assembly. The plurality of back side conductive components may be etched monolithic structures and further comprise a back side routing layer and an interconnection element integrally formed with the back side routing layer and extending in a direction away from the back side routing layer. The back side routing layer of at least one of the plurality of back side conductive components overlies the rear surface of the microelectronic element. An encapsulant may be disposed between each interconnection element. The back side routing layer of the at least one of the plurality of back side conductive components extends along one of the opposed interconnection surfaces.

公开(公告)号：US10181447B2

公开(公告)日：2019-01-15

申请号：US15493917

申请日：2017-04-21

Applicant: Invensas Corporation

Inventor： Chok J. Chia ,  Qwai H. Low ,  Patrick Variot

IPC: H01L23/00 ,  H01L23/31 ,  H01L21/56 ,  H01L21/52 ,  H01L25/065 ,  H01L23/538

Abstract: A method of making a microelectronic package includes bonding a conductive structure to a carrier so that the conductive structure overlies a rear surface of a microelectronic element disposed on the carrier and an exposed top surface of the carrier. The conductive structure may be a monolithic structure having a base and a plurality of interconnections extending continuously away from the base toward the carrier. The plurality of interconnections may have free ends that overlie the carrier. The microelectronic element may be positioned between at least two adjacent interconnections of the plurality of interconnections. The plurality of interconnections and the microelectronic element may be encapsulated with an encapsulant. The carrier may be removed to expose the free ends of the interconnections and bond pads of the microelectronic element. The free ends of the interconnections and the bond pads of the microelectronic element may be conductively connected with the terminals of the microelectronic package. The conductive structure may be patterned to form external contacts. At least some of the external contacts may overlie the microelectronic element.

公开(公告)号：US20220139846A1

公开(公告)日：2022-05-05

申请号：US17509887

申请日：2021-10-25

Applicant: Invensas Corporation

Inventor： Patrick Variot ,  Hong Shen

IPC: H01L23/552 ,  H01L23/31 ,  H01L23/522

Abstract: A microelectronic device may include a substrate, a first chip on the substrate, and a second chip on the substrate. A plurality of pillars may be located between the first chip and the second chip, wherein a first end of each pillar of the plurality of pillars is adjacent to the substrate. A spacing among the plurality of pillars is at least equal to a distance sufficient to block electromagnetic interference (EMI) and/or radio frequency interference (RFI) between the first chip and the second chip. The microelectronic device may also include a cover over at least the first chip, the second chip, and the plurality of pillars, wherein a second end of each pillar of the plurality of pillars is at least adjacent to a trench defined within the cover. The trench may include a conductive material therein.

公开(公告)号：US20190148324A1

公开(公告)日：2019-05-16

申请号：US16245925

申请日：2019-01-11

Applicant: Invensas Corporation

Inventor： Chok J. Chia ,  Qwai H. Low ,  Patrick Variot

IPC: H01L23/00 ,  H01L23/538 ,  H01L23/31 ,  H01L25/065 ,  H01L21/52 ,  H01L21/56

Abstract: A method of making a microelectronic package includes bonding a conductive structure to a carrier. The conductive structure can include a base and a plurality of interconnections extending continuously away from the base toward the carrier. The microelectronic element can be positioned between at least two adjacent interconnections of the plurality of interconnections. The conductive structure may be bonded to the carrier so that the conductive structure overlies a rear surface of a microelectronic element disposed on the carrier and an exposed top surface of the carrier. The plurality of interconnections and the microelectronic element may be encapsulated. The carrier may be removed to expose free ends of the interconnections and bond pads of the microelectronic element. The free ends of the interconnections and bond pads of the microelectronic element may be conductively connected with terminals of the microelectronic package. The conductive structure may be patterned to form external contacts.