Invention Grant
- Patent Title: Minimizing phase mismatch and offset sensitivity in a dual-path system
-
Application No.: US16121259Application Date: 2018-09-04
-
Publication No.: US11047890B2Publication Date: 2021-06-29
- Inventor: Gautham S. Sivasankar , Tejasvi Das , Emmanuel Marchais , Amar Vellanki , Leyi Yin , John L. Melanson , Venugopal Choukinishi
- Applicant: Cirrus Logic International Semiconductor Ltd.
- Applicant Address: GB Edinburgh
- Assignee: Cirrus Logic International Semiconductor Ltd.
- Current Assignee: Cirrus Logic International Semiconductor Ltd.
- Current Assignee Address: GB Edinburgh
- Agency: Jackson Walker L.L.P.
- Main IPC: G01R25/00
- IPC: G01R25/00 ; H03D13/00 ; H03F3/183 ; H03G3/30 ; H04R3/00 ; H03G3/00 ; G01R19/25 ; G01R21/133 ; G01R29/18 ; G01R31/317 ; G01R31/30 ; G01R19/04
Abstract:
A method of determining a phase misalignment between a first signal generated from a first signal path and a second signal generated from a second signal path may include obtaining multiple samples of the first signal proximate to when the first signal crosses zero wherein the first signal can be approximated as linear; obtaining multiple samples of the second signal proximate to when the second signal crosses zero wherein the first signal can be approximated as linear; based on the multiple samples of the first signal, approximating a first time at which the first signal crosses zero; based on the multiple samples of the second signal, approximating a second time at which the second signal crosses zero; and determining the phase misalignment between the first signal and the second signal based on a difference between the first time and the second time.
Public/Granted literature
- US20190257866A1 MINIMIZING PHASE MISMATCH AND OFFSET SENSITIVITY IN A DUAL-PATH SYSTEM Public/Granted day:2019-08-22
Information query
