Single-inductor multiple output (SIMO) switching power supply having offset common-mode voltage for operating a class-d audio amplifier

    公开(公告)号:US11552567B2

    公开(公告)日:2023-01-10

    申请号:US17218992

    申请日:2021-03-31

    IPC分类号: H02M3/158 H03F3/217 H02M1/00

    摘要: A single-inductor multiple output (SIMO) switched-power DC-DC converter for a class-D amplifier provides outputs that are symmetric about a common-mode input voltage of the amplifier, while remaining asymmetric about a return terminal of the amplifier and switching converter. The DC-DC converter includes an inductive element, a switching circuit that energizes the inductive element from an input source, and a control circuit that controls the switching circuit. The control circuit may have multiple switching modes, and in one of the multiple switching modes, the switching circuit may couple the inductive element between outputs of the converter so that stored energy produces a differential change between the voltages of the outputs. The control circuit may implement a first control loop that maintains a common mode voltage of the pair of outputs at a predetermined voltage independent of the individual voltages of the pair of outputs.

    DEVICE CALBRATION FOR ISOCHRONOUS CHANNEL COMMUNICATION

    公开(公告)号:US20220231775A1

    公开(公告)日:2022-07-21

    申请号:US17150170

    申请日:2021-01-15

    IPC分类号: H04J3/06 H04L12/40 H04B1/40

    摘要: Calibration of devices communicating on a shared data bus may improve data integrity on the shared data bus by reducing duty cycle distortion. Duty cycle distortion may be reduced by adjusting timing of a transceiver in a device for communicating on the shared data bus using calibration codes. The calibration codes may be loaded into memory and used to reconfigure the transceiver timing on the shared data bus with reconfiguration occurring within one or more unit-intervals of time. The calibration code may be used, for example, to adjust a PMOS or NMOS trim circuit at the transceiver.

    SYSTEM AND METHOD FOR SEMICONDUCTOR DEVICE RANDOM TELEGRAPH SEQUENCE NOISE TESTING

    公开(公告)号:US20220221505A1

    公开(公告)日:2022-07-14

    申请号:US17148371

    申请日:2021-01-13

    IPC分类号: G01R31/26 G01R31/28

    摘要: A method for screening a semiconductor device for production of excessive random telegraph sequence (RTS) noise includes measuring noise of the semiconductor device at a first temperature, changing the temperature of the semiconductor device to a second temperature different from the first temperature, measuring noise of the semiconductor device at the second temperature, extracting a characteristic of the measured noise at the first and second temperatures (e.g., standard deviation, HMM output, frequency domain spectrum of time domain noise measurement), making a comparison of the extracted first and second noise characteristics, and making a determination whether the semiconductor device produces excessive RTS noise based on whether the comparison is above a predetermined threshold. Two different bias conditions of the device may be employed rather than, or in addition to, the two different temperatures.

    Driver circuitry
    4.
    发明授权

    公开(公告)号:US11296598B1

    公开(公告)日:2022-04-05

    申请号:US17192990

    申请日:2021-03-05

    IPC分类号: H02M3/07 H02M3/156

    摘要: Driver circuitry for driving a load based on an input signal, comprising: at least one variable boost stage comprising: first and second input nodes configured to receive a first voltage and a second voltage respectively; first and second flying capacitor nodes for connection to a flying capacitor therebetween; a network of switching paths for selectively connecting the first and second input nodes with the first and second flying capacitor nodes; an output stage for selectively connecting a driver output node to each of the first and second flying capacitor nodes; and a controller operable in a first boost mode to: control the output stage to selectively connect the driver output node to the first flying capacitor node; control the network of switching paths to switch connection of the second flying capacitor node between the first and second input nodes at a controlled duty cycle; and in a first charge top-up cycle, control the network of switching paths to connect the first input node to the first flying capacitor node during a phase of the controlled duty cycle in which the first input node is connected to the second flying capacitor node; wherein the frequency of the controlled duty cycle is a greater than the frequency of the charge top-up cycle.

    Surface speaker
    6.
    发明授权

    公开(公告)号:US11228840B2

    公开(公告)日:2022-01-18

    申请号:US16040853

    申请日:2018-07-20

    IPC分类号: H04R7/04

    摘要: Embodiments described herein provide an audio device and a method of operating the audio device. The audio device comprises at least one surface, a first surface transducer positioned to excite first modes of oscillation in a first surface of the at least one surface, and a second surface transducer positioned to excite second modes of oscillation in a second surface of the at least one surface, wherein the first modes of oscillation are of a higher frequency than the second modes of oscillation.

    DYNAMIC STABILITY CONTROL IN AMPLIFIER DRIVING HIGH Q LOAD

    公开(公告)号:US20210249998A1

    公开(公告)日:2021-08-12

    申请号:US16786956

    申请日:2020-02-10

    IPC分类号: H03F1/34

    摘要: A dynamically stabilizable amplifier drives an output current into an RLC load. A driver stage generates the output current, and a control circuit compares a current level of the amplifier output with a threshold and selectively enables a stabilizing resistor (to selectively shunt the load or dampen in series with the load, depending on RLC load type) at the driver stage output based on the comparison so that the amplifier is stable across a range of the output current level. The control circuit disables the resistor when the output current is above the highest threshold and enables it when below. The control circuit may control the resistor to have one of multiple resistance values based on a comparison with multiple thresholds. The output current level may be determined by replicating the output current level or by an input current level that sets the output current level independent of the load.

    Current digital-to-analog converter with warming of digital-to-analog converter elements

    公开(公告)号:US11043959B1

    公开(公告)日:2021-06-22

    申请号:US16942062

    申请日:2020-07-29

    IPC分类号: H03M1/74 H04R3/00 H03M3/00

    摘要: A differential output current digital-to-analog (IDAC) circuit may include a delta-sigma modulator configured to receive a digital input signal, a control circuit responsive to the delta-sigma modulator configured to perform a DAC decode operation, a plurality of DAC elements responsive to the DAC decode operation, the plurality of DAC elements configured to, in concert, generate a differential output current signal based on the digital input signal to a load coupled to a pair of output terminals of the IDAC, and a plurality of warming switches, each warming switch coupled to a respective bias transistor of a respective DAC element of the plurality of DAC elements, wherein the control circuit may further be configured to selectively control each such warming switch in order to selectively de-bias and bias a respective bias transistor of such warming switch when a respective DAC element of the respective bias transistor is output-disabled from generating the differential output current signal.

    Probability-based synchronization of a serial code stream

    公开(公告)号:US10897268B2

    公开(公告)日:2021-01-19

    申请号:US16795045

    申请日:2020-02-19

    摘要: A system may include a modulator configured to generate a modulated data stream of samples from an input signal wherein each value of data in the modulated data stream when encoded is represented by a multi-bit code, wherein the modulator comprises a quantizer configured to quantize the modulated data stream from the input signal and feed back the modulated data stream as a feedback signal to an input of the modulator and a memory configured to store one or more samples of the modulated data stream. The system may also include an encoder configured to generate a synchronized serialized code stream from the modulated data stream. The quantizer may be configured to, based on the one or more samples of the modulated data stream stored in the memory, constrain the modulated data stream such that a synchronization state of the synchronized serialized code stream generated by the encoder is determinable based on the synchronized serialized code stream.