Invention Grant
- Patent Title: Semiconductor devices with through silicon vias and package-level configurability
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Application No.: US16590595Application Date: 2019-10-02
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Publication No.: US11056467B2Publication Date: 2021-07-06
- Inventor: Kevin G. Duesman , James E. Davis , Warren L. Boyer
- Applicant: Micron Technology, Inc.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Perkins Coie LLP
- Main IPC: H01L25/065
- IPC: H01L25/065 ; H01L23/00 ; H01L27/02 ; H01L25/00 ; H01L23/498 ; H01L23/60 ; H01L23/48 ; H01L23/538 ; H01L23/482

Abstract:
A semiconductor device assembly includes a substrate and a die coupled to the substrate, the die including a first contact pad electrically coupled to a first circuit on the die including an active circuit element, a first TSV electrically coupling the first contact pad to a first backside contact pad, and a second contact pad electrically coupled to a second circuit including only passive circuit elements. The substrate includes a substrate contact electrically coupled to the first and second contact pads. The assembly can further include a second die including a third contact pad electrically coupled to a third circuit including a second active circuit element, and a fourth contact pad electrically coupled to a fourth circuit on the second die including only passive circuit elements. The substrate contact can be electrically coupled to the third contact pad, but electrically disconnected from the fourth contact pad.
Public/Granted literature
- US20200035650A1 SEMICONDUCTOR DEVICES WITH THROUGH SILICON VIAS AND PACKAGE-LEVEL CONFIGURABILITY Public/Granted day:2020-01-30
Information query
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