Invention Grant
- Patent Title: Double clock architecture for small duty cycle DC-DC converter
-
Application No.: US16559118Application Date: 2019-09-03
-
Publication No.: US11057028B2Publication Date: 2021-07-06
- Inventor: Alessandro Bertolini , Alberto Cattani , Stefano Ramorini , Alessandro Gasparini
- Applicant: STMicroelectronics S.r.l.
- Applicant Address: IT Agrate Brianza
- Assignee: STMicroelectronics S.r.l.
- Current Assignee: STMicroelectronics S.r.l.
- Current Assignee Address: IT Agrate Brianza
- Agency: Crowe & Dunlevy
- Main IPC: H03K3/017
- IPC: H03K3/017 ; H03K5/04 ; H03K7/08 ; H03K5/156 ; H02M3/158

Abstract:
A DC-DC converter includes clock generation circuitry generating first and second clock signals that are out of phase, and a control signal generator generating a switching control signal at an edge of the second clock signal based upon a comparison of an error voltage to a summed voltage. Boost circuitry charges an energy storage component during an on-phase and discharges the energy storage component during an off-phase to thereby generate an output voltage. The on-phase and off-phase are set as a function of the switching control signal. Sum voltage generation circuitry generates a ramp voltage in response to an edge of the first clock signal and generates the summed voltage at an edge of the second clock signal. The sum voltage represents a sum of the ramp voltage and a voltage representative of the current flowing in the energy storage component during the on-phase.
Public/Granted literature
- US20210067148A1 DOUBLE CLOCK ARCHITECTURE FOR SMALL DUTY CYCLE DC-DC CONVERTER Public/Granted day:2021-03-04
Information query
IPC分类: