- 专利标题: Failure-atomic logging for persistent memory systems with cache-coherent FPGAs
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申请号: US16256571申请日: 2019-01-24
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公开(公告)号: US11068400B2公开(公告)日: 2021-07-20
- 发明人: Aasheesh Kolli , Irina Calciu , Jayneel Gandhi , Pratap Subrahmanyam
- 申请人: VMware, Inc.
- 申请人地址: US CA Palo Alto
- 专利权人: VMware, Inc.
- 当前专利权人: VMware, Inc.
- 当前专利权人地址: US CA Palo Alto
- 代理机构: Patterson + Sheridan, LLP
- 主分类号: G06F12/0831
- IPC分类号: G06F12/0831 ; G06F12/109 ; G06F9/50 ; G06F11/07 ; G06F12/0817
摘要:
Disclosed is a technique in which an application can record changes it makes to physical memory. In the technique, the application specifies a virtual memory region which is converted to a plurality of cache lines, each of which is monitored for changes by a device connected to a coherence interconnect coupled to the processor caches. The application sends a start signal to start the logging process and an end signal to stop the process. During the logging process, when a change occurs to one of the cache lines, an undo entry corresponding to the change is created and entered into a transaction log residing in persistent memory. The transaction log containing the undo entries makes the set of changes recorded in the transaction log atomic. If a failure occurs, the recorded changes can be undone as if they never occurred.
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