Invention Grant
- Patent Title: Dielectric barrier at non-volatile memory tile edge
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Application No.: US16459419Application Date: 2019-07-01
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Publication No.: US11069855B2Publication Date: 2021-07-20
- Inventor: Kevin L. Baker , Robert K. Grubbs , Farrell M. Good , Ervin T. Hill , Bhumika Chhabra , Jay S. Brown
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Compass IP Law, PC
- Main IPC: H01L47/00
- IPC: H01L47/00 ; H01L45/00 ; H01L27/24

Abstract:
An oxidation barrier for non-volatile memory with materials sensitive to temperature and/or cross contamination (e.g., chalcogenide materials) are described The barrier can be formed, for example, around the boundaries of a non-volatile memory tile (also known as a block or sub-array). For example, a non-volatile memory device can include an oxidation barrier on a side wall of a trench between adjacent memory tiles.
Public/Granted literature
- US20210005810A1 DIELECTRIC BARRIER AT NON-VOLATILE MEMORY TILE EDGE Public/Granted day:2021-01-07
Information query
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