Invention Grant
- Patent Title: Hybrid finfet structure with bulk source/drain regions
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Application No.: US16344003Application Date: 2016-12-12
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Publication No.: US11075286B2Publication Date: 2021-07-27
- Inventor: Chia-Hong Jan , Walid M. Hafez , Neville L. Dias , Rahul Ramaswamy , Hsu-Yu Chang , Roman W. Olac-Vaw , Chen-Guan Lee
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Schwabe, Williamson & Wyatt, P.C.
- International Application: PCT/US2016/066224 WO 20161212
- International Announcement: WO2018/111223 WO 20180621
- Main IPC: H01L29/66
- IPC: H01L29/66 ; H01L29/78 ; H01L29/739 ; H01L29/08 ; H01L29/10

Abstract:
A transistor including a source and a drain each formed in a substrate; a channel disposed in the substrate between the source and drain, wherein the channel includes opposing sidewalls with a distance between the opposing sidewalls defining a width dimension of the channel and wherein the opposing sidewalls extend a distance below a surface of the substrate; and a gate electrode on the channel. A method of forming a transistor including forming a source and a drain in an area of a substrate; forming a source contact on the source and a drain contact on the drain; after forming the source contact and the drain contact, forming a channel in the substrate in an area between the source and drain, the channel including a body having opposing sidewalls separated by a length dimension; and forming a gate contact on the channel.
Public/Granted literature
- US20190237564A1 HYBRID FINFET STRUCTURE WITH BULK SOURCE/DRAIN REGIONS Public/Granted day:2019-08-01
Information query
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