Invention Grant
- Patent Title: Lithography simulation method
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Application No.: US16584396Application Date: 2019-09-26
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Publication No.: US11080458B2Publication Date: 2021-08-03
- Inventor: Fu An Tien , Hsu-Ting Huang , Ru-Gun Liu , Shih-Hsiang Lo
- Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Applicant Address: TW Hsinchu
- Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Current Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Current Assignee Address: TW Hsinchu
- Agency: McDermott Will & Emery LLP
- Main IPC: G06F30/30
- IPC: G06F30/30 ; G06F30/398 ; G03F7/20 ; G01N21/95 ; G03F1/36 ; G06F30/3308 ; G06F30/337 ; G06F30/20 ; G06F119/18 ; G03F1/70

Abstract:
In a method of optimizing a lithography model in a lithography simulation, a mask is formed in accordance with a given layout, a wafer is printed using the mask, a pattern formed on the printed wafer is measured, a wafer pattern is simulated using a wafer edge bias table and the given mask layout, a difference between the simulated wafer pattern and the measured pattern is obtained, and the wafer edge table is adjusted according to the difference.
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