公开(公告)号：US12222641B2

公开(公告)日：2025-02-11

申请号：US17773668

申请日：2021-11-08

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Jianfang He ,  Yayi Wei ,  Yajuan Su ,  Lisong Dong ,  Libin Zhang ,  Rui Chen ,  Le Ma

IPC: G03F1/70 ,  G03F1/44 ,  G03F7/00

Abstract: The present disclosure provides a method for optimizing mask parameters, and the method includes: acquiring a test pattern, light source parameters, and initial mask parameters, the initial mask parameters including a mask thickness and an initial mask sidewall angle; generating multiple sets of candidate mask parameters according to the initial mask sidewall angle in the initial mask parameters; the multiple sets of candidate mask parameters including different mask sidewall angles and the same mask thickness; obtaining an imaging contrast of each set of candidate mask parameters based on the test pattern and the light source parameters; and selecting an optimal mask sidewall angle from the multiple sets of candidate mask parameters according to the imaging contrasts. By generating multiple sets of candidate mask parameters including different mask sidewall angles and the same mask thickness, and simulating these sets of candidate mask parameters respectively, the imaging contrast of each set of candidate mask parameters is obtained, so that the optimal mask sidewall angle is found according to the imaging contrasts. Therefore, by optimizing the mask parameters of the multi-layer film lens structure, the imaging contrast can also be significantly improved, and the imaging resolution can be improved.

公开(公告)号：US20250044708A1

公开(公告)日：2025-02-06

申请号：US18920346

申请日：2024-10-18

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Ru-Gun LIU ,  Huicheng CHANG ,  Chia-Cheng CHEN ,  Jyu-Horng SHIEH ,  Liang-Yin CHEN ,  Shu-Huei SUEN ,  Wei-Liang LIN ,  Ya Hui CHANG ,  Yi-Nien SU ,  Yung-Sung YEN ,  Chia-Fong CHANG ,  Ya-Wen YEH ,  Yu-Tien SHEN

IPC: G03F7/00 ,  G03F1/22 ,  G03F1/36 ,  G03F1/70 ,  G03F7/40 ,  H01L21/027

Abstract: In a method of forming a pattern, a photo resist layer is formed over an underlying layer, the photo resist layer is exposed to an actinic radiation carrying pattern information, the exposed photo resist layer is developed to form a developed resist pattern, a directional etching operation is applied to the developed resist pattern to form a trimmed resist pattern, and the underlying layer is patterned using the trimmed resist pattern as an etching mask.

公开(公告)号：US20250028235A1

公开(公告)日：2025-01-23

申请号：US18643392

申请日：2024-04-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Heungsuk OH ,  Hun KANG ,  Sangwook KIM ,  Sanghun KIM ,  Sujin OH ,  Jinseok OH

IPC: G03F1/36 ,  G03F1/70 ,  G06F30/392 ,  G06F119/18

Abstract: Provided are an optical proximity correction (OPC) method capable of maintaining full-chip bias consistency and a mask manufacturing method including the OPC method. The OPC method includes obtaining a first optical proximity corrected (OPCed) design layout by implementing a first OPC on an OPC target design layout; performing a reverse dissection on the OPC target design layout based on the first OPCed design layout to generate first segments; performing a reverse correction to allocate first biases of the first OPCed design layout to the first segments of the OPC target design layout; determining a full-chip representative bias based on a segment grouping of the first segments; applying the full-chip representative bias to an entire chip area; preparing mask data based on the full-chip representative bias that has been applied to the entire chip area; and exposing a mask substrate based on the mask data.

公开(公告)号：US12181793B1

公开(公告)日：2024-12-31

申请号：US17216056

申请日：2021-03-29

Applicant: Synopsys, Inc.

Inventor： Peng Liu

IPC: G06N3/00 ,  G03F1/36 ,  G03F1/70 ,  G06N3/045 ,  G06N3/08

Abstract: A tensor-based computing platform performs mask synthesis. A method includes accessing a layout of a lithographic mask and estimating a printed pattern resulting from use of the lithographic mask in a lithographic process. The lithographic process is modeled by a sequence of at least two forward models. A first of the forward models uses the layout of the lithographic mask as input and a last of the forward models produces the estimated printed pattern as output. The method further includes modifying the layout of the lithographic mask based on differences between the estimated printed pattern and a target printed pattern. All of the forward models are implemented on the tensor-based computing platform.

公开(公告)号：US12159092B2

公开(公告)日：2024-12-03

申请号：US18226677

申请日：2023-07-26

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Chia-Ping Chiang ,  Ming-Hui Chih ,  Chih-Wei Hsu ,  Ping-Chieh Wu ,  Ya-Ting Chang ,  Tsung-Yu Wang ,  Wen-Li Cheng ,  Hui En Yin ,  Wen-Chun Huang ,  Ru-Gun Liu ,  Tsai-Sheng Gau

IPC: G06F30/39 ,  G03F1/70 ,  G03F7/00

Abstract: Implementations of the present disclosure provide coloring methods that sort and pre-color nodes of G0-linked networks in a multiple-patterning technology (MPT)-compliant layout design by coordinate. In one embodiment, a method includes identifying target networks in a circuit layout, each target network having two or more linked nodes representing circuit patterns, and each target network being presented in an imaginary X-Y coordinate plane, assigning a first feature to a first node in each target network, the first node is determined using a coordinate-based method, and assigning the first feature and a second feature to remaining nodes in each target network in an alternating manner so that any two immediately adjacent linked nodes in each target network have different features.

公开(公告)号：US20240370635A1

公开(公告)日：2024-11-07

申请号：US18774614

申请日：2024-07-16

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Shih-Wei PENG ,  Jiann-Tyng TZENG ,  Wei-Cheng LIN

IPC: G06F30/398 ,  G03F1/36 ,  G03F1/70 ,  G09G3/3208 ,  H01L27/118 ,  H01L27/12 ,  H10K59/131 ,  H10K59/35

Abstract: An IC device includes a gate extending along a first axis, a first channel extending through the gate along a second perpendicular axis at a first elevation along a third axis perpendicular to the first and second axes, first and second source/drain (S/D) structures adjacent to opposite ends of the first channel at the first elevation, a second channel extending through the gate along the second axis at a second elevation along the third axis, and third and fourth S/D structures adjacent to opposite ends of the second channel at the second elevation. Each of one of the first or third and one of the second or fourth S/D structures extends along a first segment of the first axis, and each of the other of the first or third and second or fourth S/D structures extends along a second segment of the first axis different from the first segment.

公开(公告)号：US20240330564A1

公开(公告)日：2024-10-03

申请号：US18741003

申请日：2024-06-12

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Jung-Chan YANG ,  Hui-Zhong ZHUANG ,  Ting-Wei CHIANG ,  Chi-Yu LU

IPC: G06F30/398 ,  G03F1/36 ,  G03F1/70 ,  G06F30/30 ,  G06F30/392 ,  G06F30/394 ,  G06F30/3953 ,  G06F119/18

CPC classification number: G06F30/398 ,  G03F1/36 ,  G03F1/70 ,  G06F30/30 ,  G06F30/392 ,  G06F30/394 ,  G06F30/3953 ,  G06F2119/18

Abstract: A semiconductor device includes a plurality of active regions extending in a first direction. The semiconductor device further includes a gate electrode over the plurality of active regions, wherein the gate electrode extends in a second direction perpendicular to the first direction. The semiconductor device further includes a power rail extending in the first direction. The power rail includes a first power rail portion adjacent to the first boundary, wherein the first power rail portion has a first inner edge, and a second power rail portion adjacent to the second boundary, wherein the second power rail portion has a second inner edge, and the first inner edge is offset from the second inner edge in the second direction.

公开(公告)号：US20240310719A1

公开(公告)日：2024-09-19

申请号：US18532757

申请日：2023-12-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jonghyun HWANG ,  Jaeil LEE ,  Kyoungcho NA

IPC: G03F1/70 ,  G03F7/00 ,  H01L21/66

CPC classification number: G03F1/70 ,  G03F7/70504 ,  G03F7/70508 ,  G03F7/70516 ,  G03F7/706 ,  H01L22/12

Abstract: An overlay correction method for improving an overlay parameter of an ultra-high order component includes: obtaining misalignment components of an overlay through measurement; converting the misalignment components into overlay parameters; applying a conversion logic between the overlay parameters; converting the overlay parameters into aberration input data; and performing an exposure process by applying the aberration input data to an exposure machine, wherein the overlay parameters are divided into a first overlay parameter shifting in a first direction that is an extending direction of a slit, and a second overlay parameter shifting in a second direction that is perpendicular to the first direction, and the performing of the exposure process includes correcting the first and second overlay parameters including a higher-order component of a 3rd order or greater with respect to a location of the slit in the first direction.

公开(公告)号：US20240282647A1

公开(公告)日：2024-08-22

申请号：US18171729

申请日：2023-02-21

Applicant: GlobalFoundries U.S. Inc.

Inventor： Laszlo Andras Fürst ,  Ulrich Zeiske ,  Georg Gnüchtel

IPC: H01L21/66 ,  G03F1/44 ,  G03F1/70

CPC classification number: H01L22/34 ,  G03F1/44 ,  G03F1/70

Abstract: A reticle includes a body having a single-use illumination field. The single-use illumination field defines a layer including: a plurality of integrated circuit (IC) die clusters, each of the plurality of IC die clusters including a plurality of IC dies separated by a first scribe line having a first width. The plurality of IC die clusters are arranged in juxtaposition on the body and are separated by a second scribe line having a second width larger than the first width. The IC die clusters each have a same number of IC dies and a same area. There may be a different number of IC dies in an X direction than in a Y direction. The wider scribe lines are configured to include all optical or electrical test structures, and minimize effective die area. A wafer formed using the reticle and a method of forming the reticle are also provided.

公开(公告)号：US12020948B2

公开(公告)日：2024-06-25

申请号：US17377634

申请日：2021-07-16

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Yun-Jui He ,  Chih-Teng Liao

IPC: H01L21/3213 ,  G03F1/70 ,  G06F30/39

CPC classification number: H01L21/32137 ,  G03F1/70 ,  G06F30/39 ,  H01L21/32139

Abstract: Provided are methods of manufacturing integrated circuit that include a polysilicon etch process in which the wafer having an etch poly pattern is loaded into a reactor chamber and exposed to an activated etchant and, during the etch process, adjusting the temperature conditions within the reactor chamber to increase polymeric deposition on an upper surface of the wafer.