Invention Grant
- Patent Title: Non-volatile memory device and erasing method of the same
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Application No.: US17019889Application Date: 2020-09-14
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Publication No.: US11081186B2Publication Date: 2021-08-03
- Inventor: Ji-Young Lee , Young-sik Rho , Il-han Park
- Applicant: Samsung Electronics Co., Ltd.
- Applicant Address: KR Suwon-si
- Assignee: Samsung Electronics Co., Ltd.
- Current Assignee: Samsung Electronics Co., Ltd.
- Current Assignee Address: KR Suwon-si
- Agency: Harness, Dickey & Pierce, P.L.C.
- Priority: KR10-2018-0066091 20180608
- Main IPC: G11C16/06
- IPC: G11C16/06 ; G11C16/14 ; G11C16/04 ; G11C16/34 ; H01L25/065 ; H01L25/18 ; H01L23/00 ; H01L27/11556 ; H01L27/11582

Abstract:
Provided are a non-volatile memory device and an erasing method thereof. The non-volatile memory device including a memory cell region includes first metal pads and a memory block, the memory block being disposed in a memory cell region and includes a plurality of cell strings having a plurality of memory cells stacked in a direction perpendicular to a substrate between a plurality of bit line and a common source line of the memory block, and a peripheral circuit region including second metal pads and a control logic, and vertically connected to the memory cell region by the first metal pads and the second metal pads, wherein the control logic configured to, perform control such that a first erase voltage is provided to the plurality of bit lines and the common source line, and a first erase control voltage is provided to a plurality of first selection lines and a second selection line during a first erase period, the plurality of first selection lines being used for selecting a corresponding cell string from among the plurality of cell strings and the second selection line being disposed closest to the common source line, and perform control such that a second erase voltage is provided to the plurality of bit lines, and such that a second erase control voltage is provided to at least one first selection line among the plurality of first selection lines during a second erase period, the second erase control voltage being lower than the first erase control voltage.
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