公开(公告)号：US11081186B2

公开(公告)日：2021-08-03

申请号：US17019889

申请日：2020-09-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ji-Young Lee ,  Young-sik Rho ,  Il-han Park

IPC: G11C16/06 ,  G11C16/14 ,  G11C16/04 ,  G11C16/34 ,  H01L25/065 ,  H01L25/18 ,  H01L23/00 ,  H01L27/11556 ,  H01L27/11582

Abstract: Provided are a non-volatile memory device and an erasing method thereof. The non-volatile memory device including a memory cell region includes first metal pads and a memory block, the memory block being disposed in a memory cell region and includes a plurality of cell strings having a plurality of memory cells stacked in a direction perpendicular to a substrate between a plurality of bit line and a common source line of the memory block, and a peripheral circuit region including second metal pads and a control logic, and vertically connected to the memory cell region by the first metal pads and the second metal pads, wherein the control logic configured to, perform control such that a first erase voltage is provided to the plurality of bit lines and the common source line, and a first erase control voltage is provided to a plurality of first selection lines and a second selection line during a first erase period, the plurality of first selection lines being used for selecting a corresponding cell string from among the plurality of cell strings and the second selection line being disposed closest to the common source line, and perform control such that a second erase voltage is provided to the plurality of bit lines, and such that a second erase control voltage is provided to at least one first selection line among the plurality of first selection lines during a second erase period, the second erase control voltage being lower than the first erase control voltage.

公开(公告)号：US10777278B2

公开(公告)日：2020-09-15

申请号：US16401877

申请日：2019-05-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ji-Young Lee ,  Young-sik Rho ,  Il-han Park

IPC: G11C16/04 ,  G11C16/14 ,  G11C16/10 ,  G11C16/34

Abstract: Provided are a non-volatile memory device and an erasing method thereof. The erasing method of the non-volatile memory device including a plurality of cell strings in which memory cells and selection transistors are connected, includes: performing a first erase operation based on an erase voltage provided to a first electrode of at least one of the selection transistors and an erase control voltage provided to a second electrode of the at least one of the selection transistors; determining whether there are slow erase cells by performing a multiple erase verify operation based on first and second verify voltages, the second verify voltage being higher than the first verify voltage; adjusting, when there are slow erase cells, the erase control voltage such that a voltage difference between the erase voltage and the erase control voltage increases; and performing a second erase operation based on the adjusted erase control voltage.

公开(公告)号：US20190378574A1

公开(公告)日：2019-12-12

申请号：US16401877

申请日：2019-05-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ji-Young LEE ,  Young-sik Rho ,  ll-han Park

IPC: G11C16/14 ,  G11C16/04 ,  G11C16/34 ,  G11C16/10

Abstract: Provided are a non-volatile memory device and an erasing method thereof. The erasing method of the non-volatile memory device including a plurality of cell strings in which memory cells and selection transistors are connected, includes: performing a first erase operation based on an erase voltage provided to a first electrode of at least one of the selection transistors and an erase control voltage provided to a second electrode of the at least one of the selection transistors; determining whether there are slow erase cells by performing a multiple erase verify operation based on first and second verify voltages, the second verify voltage being higher than the first verify voltage; adjusting, when there are slow erase cells, the erase control voltage such that a voltage difference between the erase voltage and the erase control voltage increases; and performing a second erase operation based on the adjusted erase control voltage.