Invention Grant
- Patent Title: System, apparatus and method for inter-die functional testing of an integrated circuit
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Application No.: US15801454Application Date: 2017-11-02
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Publication No.: US11105854B2Publication Date: 2021-08-31
- Inventor: Lakshminarayana Pappu , Robert P. Adler , Ki Yoon
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Trop, Pruner & Hu, P.C.
- Main IPC: G01R31/3187
- IPC: G01R31/3187 ; G01R31/3185

Abstract:
In one embodiment, an apparatus includes multiple die and at least one interconnect to couple the die. A first die includes one or more cores, a first fabric and a first fabric transactor coupled to the first fabric, the first fabric transactor to initiate a functional test of the apparatus in response to a test signal, cause at least one first test transaction to be sent to a second die, receive a first response to the at least one first test transaction from the second die, and identify, based at least in part on the first response to the at least one test transaction, a location of a failure and report the location of the failure to a destination. Other embodiments are described and claimed.
Public/Granted literature
- US20190033368A1 System, Apparatus And Method For Inter-Die Functional Testing Of An Integrated Circuit Public/Granted day:2019-01-31
Information query
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