Invention Grant
- Patent Title: Non-volatile memory read method for improving read margin
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Application No.: US16828545Application Date: 2020-03-24
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Publication No.: US11120862B2Publication Date: 2021-09-14
- Inventor: Koichi Takeda
- Applicant: RENESAS ELECTRONICS CORPORATION
- Applicant Address: JP Tokyo
- Assignee: RENESAS ELECTRONICS CORPORATION
- Current Assignee: RENESAS ELECTRONICS CORPORATION
- Current Assignee Address: JP Tokyo
- Agency: McDermott Will & Emery LLP
- Priority: JPJP2019-074691 20190410
- Main IPC: G11C7/12
- IPC: G11C7/12 ; G11C11/4074 ; G11C11/4076 ; G11C11/4091 ; G11C11/4094 ; G11C11/408 ; G11C16/02 ; G11C16/26 ; G11C16/28 ; G11C16/24 ; G11C16/04

Abstract:
A semiconductor device capable of enlarging a read margin of a memory cell and a method of surrounding a read of a memory are provided. The reference word line RWL is activated in a time division manner with respect to the plurality of word lines WL. The precharge circuit PRE applies the read potential VRD to the bit line BL, and the precharge circuit PRE flows the read current Icel from the selected memory cell MC and the read reference current Iref from the reference cell RC to the bit line BL in a time division manner. A detection currents Ird2a, Irr2a, each of which is a current proportional to the current flowing through the bitline BL, flows through the current detection line CDL.
Public/Granted literature
- US20200327921A1 SEMICONDUCTOR DEVICE AND MEMORY READING METHOD Public/Granted day:2020-10-15
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