- Patent Title: Methods for threshold voltage tuning and structure formed thereby
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Application No.: US16684765Application Date: 2019-11-15
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Publication No.: US11121041B2Publication Date: 2021-09-14
- Inventor: Zoe Chen , Ching-Hwanq Su , Cheng-Lung Hung , Cheng-Yen Tsai , Da-Yuan Lee , Hsin-Yi Lee , Weng Chang , Wei-Chin Lee
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsinchu
- Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee Address: TW Hsinchu
- Agency: Slater Matsil, LLP
- Main IPC: H01L21/8238
- IPC: H01L21/8238 ; H01L27/092 ; H01L29/10

Abstract:
Generally, the present disclosure provides example embodiments relating to tuning threshold voltages in transistor devices and the transistor devices formed thereby. Various examples implementing various mechanisms for tuning threshold voltages are described. In an example method, a gate dielectric layer is deposited over an active area in a device region of a substrate. A dipole layer is deposited over the gate dielectric layer in the device region. A dipole dopant species is diffused from the dipole layer into the gate dielectric layer in the device region.
Public/Granted literature
- US20200083114A1 Methods for Threshold Voltage Tuning and Structure Formed Thereby Public/Granted day:2020-03-12
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