Invention Grant
- Patent Title: Integrated circuit stacking approach
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Application No.: US16152561Application Date: 2018-10-05
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Publication No.: US11121118B2Publication Date: 2021-09-14
- Inventor: Jing-Cheng Lin , Shang-Yun Hou
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Eschweiler & Potashnik, LLC
- Main IPC: H01L23/48
- IPC: H01L23/48 ; H01L25/065 ; H01L23/00 ; H01L23/31 ; H01L21/56 ; H01L21/48 ; H01L25/00 ; H01L23/498 ; H01L21/683 ; H01L21/60

Abstract:
The present disclosure, in some embodiments, relates to a semiconductor package. The semiconductor package includes an interposer substrate laterally surrounding through-substrate-vias. A redistribution structure is on a first surface of the interposer substrate. The redistribution structure laterally extends past an outermost sidewall of the interposer substrate. A packaged die is bonded to the redistribution structure. One or more conductive layers are arranged along a second surface of the interposer substrate opposite the first surface. A molding compound vertically extends from the redistribution structure to laterally surround the one or more conductive layers.
Public/Granted literature
- US20190088620A1 NOVEL INTEGRATED CIRCUIT STACKING APPROACH Public/Granted day:2019-03-21
Information query
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