Invention Grant
- Patent Title: Memory device with configurable error correction modes
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Application No.: US16792820Application Date: 2020-02-17
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Publication No.: US11126498B2Publication Date: 2021-09-21
- Inventor: Scott E. Schaefer , Aaron P. Boehm
- Applicant: Micron Technology, Inc.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Holland & Hart LLP
- Main IPC: H03M13/00
- IPC: H03M13/00 ; G06F11/10 ; G11C29/44 ; G11C7/10 ; G11C29/42 ; G06F11/07

Abstract:
Methods, systems, and apparatus to selectively implement single-error correcting (SEC) operations or single-error correcting and double-error detecting (SECDED) operations, without noticeably impacting die size, for information received from a host device. For example, a host device may indicate that a memory system is to implement SECDED operations using one or more communications (e.g., messages). In another example, the memory system may be hardwired to perform SECDED for certain options. The memory system may adapt circuitry associated with SEC operations to implement SECDED operations without noticeably impacting die size. To implement SECDED operations using SEC circuitry, the memory system may include some additional circuitry to repurpose the SEC circuitry for SECDED operations.
Public/Granted literature
- US20200264950A1 MEMORY DEVICE WITH CONFIGURABLE ERROR CORRECTION MODES Public/Granted day:2020-08-20
Information query
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