公开(公告)号：US12283333B2

公开(公告)日：2025-04-22

申请号：US18640651

申请日：2024-04-19

Applicant: Micron Technology, Inc.

Inventor： Scott E. Schaefer

IPC: G11C29/44 ,  G11C29/12 ,  G11C29/18 ,  G11C29/42

Abstract: Methods, systems, and devices for bit retiring to mitigate bit errors are described. A memory device may retrieve a set of bits from a first row of an address space and may determine that the set of bits includes one or more errors. The memory device may remap at least a portion of the first row from a first row index to a second row index, where the second row index, before the remapping, corresponds to a second row within the address space addressable by the host device. Additionally or alternatively, the memory device may receive a first command to access a first logical address of a memory array that is associated with a first row index. The memory device may determine that the first row includes one or more errors and may transmit a signal indicating that the first row includes the one or more errors.

公开(公告)号：US20250118388A1

公开(公告)日：2025-04-10

申请号：US18987930

申请日：2024-12-19

Applicant: Micron Technology, Inc.

Inventor： Scott E. Schaefer ,  Aaron P. Boehm

IPC: G06F11/07

Abstract: Methods, systems, and devices for metadata storage at a memory device are described to support storage of metadata information and error control information at a memory device. The metadata information and error control information may be received at the memory device via a sideband channel and corresponding pin. For example, a set of bits received via the pin may include a subset of error control bits and a subset of metadata bits. Circuitry at the memory device may receive the set of bits via the pin and may identify metadata information and error control information within the set of bits. The circuitry may route the metadata information to a corresponding subset of memory cells and the error control information to an error control circuit, where the error control circuit may route the error control information to a corresponding subset of memory cells.

公开(公告)号：US12242343B2

公开(公告)日：2025-03-04

申请号：US18049454

申请日：2022-10-25

Applicant: Micron Technology, Inc.

Inventor： Melissa I. Uribe ,  Aaron P. Boehm ,  Scott E. Schaefer ,  Steffen Buch

IPC: G06F11/10 ,  G06F11/07

Abstract: Implementations described herein relate to command address fault detection using a parity bit. A memory device may receive, from a host device via a command address (CA) bus and during a unit interval, a set of CA bits associated with a CA word. The memory device may receive, from the host device via a parity bus and during the unit interval, a first parity bit that is based on the set of CA bits and a parity generation process. The memory device may generate a second parity bit based on the set of CA bits and the parity generation process. The memory device may compare the first parity bit and the second parity bit. The memory device may selectively transmit an alert signal to the host device based on a result of comparing the first parity bit and the second parity bit.

公开(公告)号：US12237031B2

公开(公告)日：2025-02-25

申请号：US17807307

申请日：2022-06-16

Applicant: Micron Technology, Inc.

Inventor： Scott E. Schaefer

IPC: G11C29/12

Abstract: Implementations described herein relate to refresh rate selection for a memory built-in self-test. A memory device may read one or more bits, associated with the memory built-in self-test, that are stored in a mode register of the memory device. The memory device may identify, based on the one or more bits, a refresh rate to be used while performing the memory built-in self-test. The refresh rate may indicate a rate at which memory cells, to be tested by the memory built-in self-test, are to be refreshed while the memory built-in self-test is being performed. The memory device may perform the memory built-in self-test while refreshing the memory cells according to the refresh rate.

公开(公告)号：US12165740B2

公开(公告)日：2024-12-10

申请号：US17821413

申请日：2022-08-22

Applicant: Micron Technology, Inc.

Inventor： Aaron P. Boehm ,  Scott E. Schaefer ,  Scott D. Van De Graaff ,  Mark D. Ingram ,  Todd Jackson Plum

IPC: G11C7/24 ,  G11C7/04 ,  G11C7/10

Abstract: Methods, systems, and devices for memory traffic monitoring are described. The monitoring may include traffic monitoring of access operations performed at various components of the memory device, or may include sensors that may measure parameters of components of the memory device to detect wear. The traffic monitoring or the parameters measured by the sensors may be represented by a characteristic related to an operational bias of circuits of the memory device. The memory device may use the characteristic (e.g., along with a threshold) to determine whether to adjust a parameter associated with performing access operations received by the memory device, in order to implement a corrective action.

公开(公告)号：US20240403155A1

公开(公告)日：2024-12-05

申请号：US18803114

申请日：2024-08-13

Applicant: Micron Technology, Inc.

Inventor： Scott E. Schaefer

IPC: G06F11/07

Abstract: Methods, systems, and devices for error log indication via error control information are described. For instance, a memory device may transmit, to a host device, a first signal including a set of error control bits indicating that an error log of the memory device includes information for use by the host device. The memory device may receive, from the host device in response to the first signal, a second signal including a request to retrieve the information of the error log. The memory device may transmit, to the host device in response to the second signal, a third signal including the information of the error log.

公开(公告)号：US20240303157A1

公开(公告)日：2024-09-12

申请号：US18584385

申请日：2024-02-22

Applicant: Micron Technology, Inc.

Inventor： Scott E. Schaefer ,  Paul A. Laberge

IPC: G06F11/10 ,  G06F11/07

CPC classification number: G06F11/1068 ,  G06F11/0787 ,  G06F11/079

Abstract: Methods, systems, and devices for memory die fault detection using a calibration pin are described. A memory device may perform a calibration procedure on a first resistor of each of a set of memory dies of a memory module using a pin coupled with the memory module. The memory device may couple the pin to a second resistor of a memory die of the set of memory dies based on the memory die identifying a fault condition for the memory die executing one or more of multiple commands from the host device. The memory device may receive, from the host device, a command to read a register of one or more memory dies of the set of memory dies and may output, to the host device, an indication of the memory die that identified the fault condition based on coupling the pin to the second resistor.

公开(公告)号：US12066927B2

公开(公告)日：2024-08-20

申请号：US18093762

申请日：2023-01-05

Applicant: Micron Technology, Inc.

Inventor： Aaron P. Boehm ,  Todd Jackson Plum ,  Mark D. Ingram ,  Scott E. Schaefer ,  Scott D. Van De Graaff

IPC: G06F12/00 ,  G06F11/34 ,  G06F12/02

CPC classification number: G06F12/023 ,  G06F11/3495 ,  G06F2212/7211

Abstract: Methods, systems, and devices for adaptive user defined health indications are described. A host device may be configured to dynamically indicate adaptive health flags for monitoring health and wear information for a memory device. The host device may indicate, to a memory device, a first index. The first index may correspond to a first level of wear of a set of multiple indexed levels of wear for the memory device. The memory device may determine that a metric of the memory device satisfies the first level of wear and indicate, to the host device, that the first level of wear is satisfied. The host device may receive the indication that the first level of wear is satisfied and indicate, to the memory device, a second level of wear of the set of indexed levels of wear that is different than the first level of wear.

公开(公告)号：US11966602B2

公开(公告)日：2024-04-23

申请号：US18100825

申请日：2023-01-24

Applicant: Micron Technology, Inc.

Inventor： Scott E. Schaefer ,  Aaron P. Boehm

IPC: G06F3/06

CPC classification number: G06F3/0632 ,  G06F3/0604 ,  G06F3/0655 ,  G06F3/0679

Abstract: Methods, systems, and devices for refresh counters in a memory system are described. In some examples, a memory device may include two or more counters configured to increment a respective count based on refresh operations performed on a memory array. A comparison may be made between two or more of the respective counts, which may include determining a difference between the respective counts or a difference in rate of incrementing. A memory device may transmit an indication to a host device based on determining a difference between counters, and the memory device, the host device, or both, may perform various operations or enter various operational modes based on the determined difference.

公开(公告)号：US11928023B1

公开(公告)日：2024-03-12

申请号：US18050679

申请日：2022-10-28

Applicant: Micron Technology, Inc.

Inventor： Scott E. Schaefer

IPC: G06F11/10 ,  G06F11/07

CPC classification number: G06F11/1048 ,  G06F11/0793 ,  G06F11/1068

Abstract: Methods, systems, and devices for techniques for indicating a write link error are described. The method may include a memory device receiving, from a host device, a write command, data, and a first set of error control bits for the data. The memory device may determine that the data includes an uncorrectable error using the first set of error control bits and generate a second set of error control bits for the data based on determining that the data includes the uncorrectable error. Further, the method may include the memory device storing the data and the second set of error control bits in a memory device and transmitting, to the host device, the data and an indication that the data received from the host device included the uncorrectable error based on the second set of error control bits.