A stage circuit includes a first substage circuit unit connected to first through third input terminals receiving a start signal, a first clock signal, and a second clock signal, respectively. The first substage circuit unit generates first and second operation signals based on the start signal and the first and second clock signals, and supplies a first scan signal to a first output terminal based on the first and second operation signals. The stage circuit further includes a second substage circuit unit connected to the third input terminal and a fourth input terminal receiving a third clock signal. The second substage circuit unit supplies a second scan signal to a second output terminal based on the first and second operation signals, the second clock signal, and the third clock signal. The first and second scan signals include a pulse of a low voltage level and a high voltage level, respectively.