- 专利标题: Boosted return time for fast chirp PLL and calibration method
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申请号: US16426623申请日: 2019-05-30
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公开(公告)号: US11131762B2公开(公告)日: 2021-09-28
- 发明人: Jean-Stephane Vigier , Didier Salle , Cristian Pavao-Moreira , Julien Orlando
- 申请人: NXP USA, INC.
- 申请人地址: US TX Austin
- 专利权人: NXP USA, INC.
- 当前专利权人: NXP USA, INC.
- 当前专利权人地址: US TX Austin
- 优先权: EP18305686 20180606
- 主分类号: G01S13/34
- IPC分类号: G01S13/34 ; G01S7/35 ; H03L7/087 ; H03L7/18 ; H03C3/09 ; G01S7/40
摘要:
A fast chirp Phase Locked Loop with a boosted return time includes a Voltage Controlled Oscillator, VCO, generating a Frequency Modulated Continuous Waveform, FMCW. The VCO responds to a filtered output voltage of a filter connected to a charge pump. A digital controller modifies the FMCW to generate a chirp phase and a return phase. The chirp phase includes a first linear change of the FMCW from a start frequency to a stop frequency. The return phase includes a second linear change of the FMCW from the stop frequency to the start frequency. A boost circuit connects to the digital controller and the filter. The boost circuit supplies a boost current during the return phase. The boost current is proportional to a return slope of the return phase and inversely proportional to a VCO gain of the VCO.
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