公开(公告)号：US12231136B2

公开(公告)日：2025-02-18

申请号：US17655399

申请日：2022-03-18

Applicant: NXP B.V.

Inventor： Mathieu Perin ,  Stefano Dal Toso ,  Khurram Waheed ,  Claudio Gustavo Rey

IPC: H03L7/189 ,  H03C3/09 ,  H03L7/085 ,  H03L7/099 ,  H03L7/10

Abstract: A type I phase locked loop (PLL) includes an oscillator and a feedback path to a phase detector. A first frequency and first relative phase of a first output signal are locked to a frequency and a phase of a first input signal. A second frequency and second relative phase of a second output signal are locked to a frequency and a phase of a second input signal. A correction to the PLL is applied to perform one of: adjusting the second relative phase to equal the first relative phase and adjusting the oscillator frequency.

公开(公告)号：US11955979B2

公开(公告)日：2024-04-09

申请号：US17835292

申请日：2022-06-08

Applicant: Apple Inc.

Inventor： Reetika K Agarwal ,  Abbas Komijani ,  Hongrui Wang

IPC: H03L7/00 ,  H03C3/09 ,  H03L7/089 ,  H03L7/091 ,  H03L7/099 ,  H03L7/185 ,  H03L7/197 ,  H04L7/033

CPC classification number: H03L7/0891 ,  H03C3/0941 ,  H03L7/091 ,  H03L7/099 ,  H03L7/185 ,  H03L7/1976 ,  H04L7/033

Abstract: An electronic device may include wireless circuitry having mixer circuitry configured to receive oscillator signals from a partial-fractional phase-locked loop (PLL). The partial-fractional PLL may include a phase frequency detector, a charge pump, a loop filter, and a frequency divider connected in a loop. To implement the partial-fractional capability of the PLL, the frequency divider may receive a bitstream from a first order sigma delta modulator and a finite impulse response filter. The first order sigma delta modulator may output a periodic non-randomized output. The finite impulse response filter may increase the frequency of toggling of the periodic non-randomized output. Configured and operated in this way, the partial-fractional PLL can exhibit reduced phase noise.

公开(公告)号：US11437957B2

公开(公告)日：2022-09-06

申请号：US17164592

申请日：2021-02-01

Applicant: QUALCOMM Incorporated

Inventor： Zafer Boz ,  Dhammika Bokolamulla ,  Philip Jones

IPC: H03C3/09 ,  H03L7/18 ,  H04B1/10 ,  H03L7/081 ,  H03L7/099 ,  H03C3/04 ,  H03L7/10

Abstract: A receiver is provided having a two-point-modulated phase-locked loop for the rapid scanning of the signal strength of a plurality of frequency channels. The two-point modulation includes a modulation of a frequency gain by an oscillator in the phase-locked loop and a modulation of a frequency division by a divider in the phase-locked loop.

公开(公告)号：US20220247355A1

公开(公告)日：2022-08-04

申请号：US17164592

申请日：2021-02-01

Applicant: QUALCOMM Incorporated

Inventor： Zafer BOZ ,  Dhammika BOKOLAMULLA ,  Philip JONES

IPC: H03C3/09 ,  H03C3/04 ,  H03L7/081 ,  H03L7/099

Abstract: A receiver is provided having a two-point-modulated phase-locked loop for the rapid scanning of the signal strength of a plurality of frequency channels. The two-point modulation includes a modulation of a frequency gain by an oscillator in the phase-locked loop and a modulation of a frequency division by a divider in the phase-locked loop.

公开(公告)号：US11233495B2

公开(公告)日：2022-01-25

申请号：US16936148

申请日：2020-07-22

Applicant: MITSUBISHI ELECTRIC CORPORATION

Inventor： Shinya Yokomizo ,  Akihito Hirai ,  Mitsuhiro Shimozawa

IPC: H03H7/20 ,  H03C3/09 ,  H03D7/16 ,  H04B7/08 ,  H04B7/06 ,  H01Q3/36 ,  H03H11/20

Abstract: A mixer includes: a VGA (12) configured to amplify one of divided two portions of an input signal at a gain of cos θ; a VGA (13) configured to amplify another one of the divided two portions of the input signal at a gain of sin θ; an IQ generator (15) configured to input an LO wave, and output an LO wave in phase with the input LO wave and an LO wave having a phase difference of 90° with respect to the input LO wave; a mixer (16) configured to input the signal output from the VGA (12) and the LO wave which is output from the IQ generator (15), to output an RF signal; a second mixer (17) configured to input the signal from the VGA (13) and the LO wave which is output from the IQ generator, to output an RF signal; and a combiner (18).

公开(公告)号：US11112818B2

公开(公告)日：2021-09-07

申请号：US16654271

申请日：2019-10-16

Applicant: MagnaChip Semiconductor, Ltd.

Inventor： Su Hyun Kim ,  Sang Kyung Kim ,  Gil Sung Roh

IPC: H03L7/08 ,  H03L7/07 ,  G06F1/08 ,  H03C3/09

Abstract: A reception apparatus communicating with a transmission apparatus with a clock lane and a data lane. The reception apparatus comprises a clock lane control circuit configured to determine the operation mode of the clock lane based on a clock signal transmitted through the clock lane, and performing an operation based on the determined operation mode of the clock lane, and a data lane control circuit configured to determine the operation mode of the data lane based on a data signal transmitted from the transmission apparatus, and performing an operation based on the determined operation mode of the data lane, and the clock lane control circuit is configured to set the operation mode of the clock lane to a high-speed mode, when the operation mode of the data lane is switched from a low-power mode to the high-speed mode.

公开(公告)号：US20210233501A1

公开(公告)日：2021-07-29

申请号：US16752427

申请日：2020-01-24

Applicant: Intel Corporation

Inventor： Prashant Chaudhari ,  Arthur Runyan ,  Michael Derr ,  Jonathan Oder

IPC: G09G5/391 ,  G06F1/08 ,  H03C3/09 ,  H03L7/07

Abstract: Upon external display configuration change, a graphics display driver or any suitable hardware or software modifies the clock frequency of the processor core (e.g., graphics processor core) display engine. The graphics display driver or any suitable hardware or software reprograms the core display clock PLL (CDCLK PLL) to a new frequency, without any dead clocks during such frequency change. A divide-by-2 divider changes the frequency of the PLL on the fly or dynamically. The technique may not require the PLL to be turned off and turned back again at all.

公开(公告)号：US11025257B2

公开(公告)日：2021-06-01

申请号：US16744232

申请日：2020-01-16

Applicant: Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V.

Inventor： Benedikt Welp ,  Nils Pohl

IPC: H03L7/099 ,  H03B5/12 ,  H03C3/09 ,  H03L7/18 ,  H04B1/713 ,  H04L7/033 ,  H04L27/10

Abstract: An example of a device for generating a broadband frequency signal comprises a first controlled oscillator, a second controlled oscillator, a phase-locked loop for feeding back an output signal of a controlled oscillator to the corresponding controlled oscillator, and a mixer. The mixer is configured to generate the broadband frequency signal by mixing an output signal of the first controlled oscillator and an output signal of the second controlled oscillator. The device may, for example, be realized by means of a single phase-locked loop. A further example relates to a device for generating a frequency signal with a controlled oscillator and a phase-locked loop with a further controlled oscillator and a mixer in the feedback path of the phase-locked loop. Examples further relate to a high-frequency device for emitting a high-frequency signal and a method for generating a broadband frequency signal.

公开(公告)号：US20210141413A1

公开(公告)日：2021-05-13

申请号：US16779611

申请日：2020-02-02

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Dotan David Levi ,  Liron Mula ,  Ariel Almog ,  Aviad Raveh ,  Yuval Itkin

IPC: G06F1/12 ,  H03C3/09

Abstract: In one embodiment, a network interface card device includes communication interfaces to provide data connection with respective local devices configured to run respective clock synchronization clients, at least one network interface to provide data connection between a packet data network and ones of the local devices, and a hardware clock to maintain a time value, and serve the clock synchronization clients.

公开(公告)号：US10944359B2

公开(公告)日：2021-03-09

申请号：US16207751

申请日：2018-12-03

Applicant: STMicroelectronics (Grenoble 2) SAS ,  STMicroelectronics (Alps) SAS

Inventor： Benoit Marchand ,  Francois Druilhe

IPC: H03B5/12 ,  H03C3/09 ,  H03L7/099 ,  H03B5/36 ,  H03L1/02 ,  H03L7/183 ,  H03B5/04

Abstract: A quartz crystal resonator is coupled to an electronic circuit. A capacitive or resistive element is provided for adjusting a frequency of the quartz crystal resonator on activation or deactivation of a function of a circuit. Control is made according to a model of an expected variation of a temperature of the quartz crystal resonator.